src/soc/intel/denverton_ns/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 - 2017 Intel Corp.
   5  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
   6  * Copyright (C) 2018 Online SAS
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <assert.h>
  20 #include <intelblocks/gpio.h>
  21 #include <intelblocks/pcr.h>
  22 #include <soc/pcr.h>
  23 #include <soc/pm.h>
  24
  25 static const struct reset_mapping rst_map[] = {
  26         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  27         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  28         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  29         /* (applicable only for GPD group) */
  30         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  31 };
  32
  33 static const struct pad_group dnv_community_nc_groups[] = {
  34         INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ3_N),
  35         INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ4_N, NORTH_ALL_MEMHOT_N),
  36 };
  37
  38 static const struct pad_group dnv_community_sc_dfx_groups[] = {
  39         INTEL_GPP(SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT15),
  40 };
  41
  42 static const struct pad_group dnv_community_sc0_groups[] = {
  43         INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA0_LED_N),
  44         INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA1_LED_N, SOUTH_GROUP0_DFX_SPARE4),
  45 };
  46
  47 static const struct pad_group dnv_community_sc1_groups[] = {
  48         INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_STROBE),
  49         INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_CLK, SOUTH_GROUP1_GPIO_3),
  50 };
  51
  52 static const struct pad_community dnv_gpio_communities[] = {
  53         {
  54                 .port = PID_GPIOCOM1,
  55                 .first_pad = SOUTH_GROUP1_SUSPWRDNACK,
  56                 .last_pad = SOUTH_GROUP1_GPIO_3,
  57                 .num_gpi_regs = NUM_SC1_GPI_REGS,
  58                 .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +
  59                                      NUM_SC0_GPI_REGS,
  60                 .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET,
  61                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN,
  62                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS,
  63                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN,
  64                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  65                 .name = "GPIO_GPE_SC1",
  66                 .acpi_path = "\\_SB.GPO3",
  67                 .reset_map = rst_map,
  68                 .num_reset_vals = ARRAY_SIZE(rst_map),
  69                 .groups = dnv_community_sc1_groups,
  70                 .num_groups = ARRAY_SIZE(dnv_community_sc1_groups),
  71         }, {
  72                 .port = PID_GPIOCOM1,
  73                 .first_pad = SOUTH_GROUP0_SMB3_CLTT_DATA,
  74                 .last_pad = SOUTH_GROUP0_DFX_SPARE4,
  75                 .num_gpi_regs = NUM_SC0_GPI_REGS,
  76                 .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS,
  77                 .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET,
  78                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN,
  79                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS,
  80                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN,
  81                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  82                 .name = "GPIO_GPE_SC0",
  83                 .acpi_path = "\\_SB.GPO2",
  84                 .reset_map = rst_map,
  85                 .num_reset_vals = ARRAY_SIZE(rst_map),
  86                 .groups = dnv_community_sc0_groups,
  87                 .num_groups = ARRAY_SIZE(dnv_community_sc0_groups),
  88         }, {
  89                 .port = PID_GPIOCOM1,
  90                 .first_pad = SOUTH_DFX_DFX_PORT_CLK0,
  91                 .last_pad = SOUTH_DFX_DFX_PORT15,
  92                 .num_gpi_regs = NUM_SC_DFX_GPI_REGS,
  93                 .gpi_status_offset = NUM_NC_GPI_REGS,
  94                 .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET,
  95                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN,
  96                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS,
  97                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN,
  98                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  99                 .name = "GPIO_GPE_SC_DFX",
 100                 .acpi_path = "\\_SB.GPO1",
 101                 .reset_map = rst_map,
 102                 .num_reset_vals = ARRAY_SIZE(rst_map),
 103                 .groups = dnv_community_sc_dfx_groups,
 104                 .num_groups = ARRAY_SIZE(dnv_community_sc_dfx_groups),
 105         }, {
 106                 .port = PID_GPIOCOM0,
 107                 .first_pad = NORTH_ALL_GBE0_SDP0,
 108                 .last_pad = NORTH_ALL_MEMHOT_N,
 109                 .num_gpi_regs = NUM_NC_GPI_REGS,
 110                 .gpi_status_offset = 0,
 111                 .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET,
 112                 .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN,
 113                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS,
 114                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN,
 115                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 116                 .name = "GPIO_GPE_NC",
 117                 .acpi_path = "\\_SB.GPO0",
 118                 .reset_map = rst_map,
 119                 .num_reset_vals = ARRAY_SIZE(rst_map),
 120                 .groups = dnv_community_nc_groups,
 121                 .num_groups = ARRAY_SIZE(dnv_community_nc_groups),
 122         }
 123 };
 124
 125 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 126 {
 127         *num_communities = ARRAY_SIZE(dnv_gpio_communities);
 128         return dnv_gpio_communities;
 129 }