src/mainboard/lenovo/g505s/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "mainboard.h"
   4
   5 /* DefinitionBlock Statement */
   6 #include <acpi/acpi.h>
   7 DefinitionBlock (
   8         "dsdt.aml",
   9         "DSDT",
  10         ACPI_DSDT_REV_2,
  11         OEM_ID,
  12         ACPI_TABLE_CREATOR,
  13         0x00010001              /* OEM Revision */
  14         )
  15 {       /* Start of ASL file */
  16
  17         /* Globals for the platform */
  18         #include "acpi/mainboard.asl"
  19
  20         /* Describe the USB Overcurrent pins */
  21         #include "acpi/usb_oc.asl"
  22
  23         /* PCI IRQ mapping for the Southbridge */
  24         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  25
  26         /* Describe the processor tree (\_SB) */
  27         #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
  28
  29         /* Describe the supported Sleep States for this Southbridge */
  30         #include <southbridge/amd/common/acpi/sleepstates.asl>
  31
  32         /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
  33         #include "acpi/sleep.asl"
  34
  35         Scope(\_SB) {
  36                 /* global utility methods expected within the \_SB scope */
  37                 #include <arch/x86/acpi/globutil.asl>
  38
  39                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  40                 #include "acpi/routing.asl"
  41
  42                 Device(PCI0) {
  43                         /* Describe the AMD Northbridge */
  44                         #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
  45
  46                         /* Describe the AMD Fusion Controller Hub Southbridge */
  47                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  48
  49                 }
  50
  51                 /* Describe PCI INT[A-H] for the Southbridge */
  52                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  53
  54         }   /* End Scope(_SB) */
  55
  56         Scope(\_SB.PCI0.LIBR) {
  57                 #include "acpi/ec.asl"
  58         }
  59
  60         /* Describe SMBUS for the Southbridge */
  61         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  62
  63         /* Define the General Purpose Events for the platform */
  64         #include "acpi/gpe.asl"
  65
  66         /* Define the Thermal zones and methods for the platform */
  67         #include "acpi/thermal.asl"
  68
  69         /* Define the System Indicators for the platform */
  70         #include "acpi/si.asl"
  71
  72 }
  73 /* End of ASL file */