src/mainboard/asrock/imb-a180/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* DefinitionBlock Statement */
   4 #include <acpi/acpi.h>
   5 DefinitionBlock (
   6         "dsdt.aml",
   7         "DSDT",
   8         ACPI_DSDT_REV_2,
   9         OEM_ID,
  10         ACPI_TABLE_CREATOR,
  11         0x00010001      /* OEM Revision */
  12         )
  13 {       /* Start of ASL file */
  14
  15         /* Globals for the platform */
  16         #include "acpi/mainboard.asl"
  17
  18         /* Describe the USB Overcurrent pins */
  19         #include "acpi/usb_oc.asl"
  20
  21         /* PCI IRQ mapping for the Southbridge */
  22         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  23
  24         /* Describe the processor tree (\_SB) */
  25         #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
  26
  27         /* Contains the supported sleep states for this chipset */
  28         #include <southbridge/amd/common/acpi/sleepstates.asl>
  29
  30         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  31         #include "acpi/sleep.asl"
  32
  33         /* System Bus */
  34         Scope(\_SB) { /* Start \_SB scope */
  35                 /* global utility methods expected within the \_SB scope */
  36                 #include <arch/x86/acpi/globutil.asl>
  37
  38                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  39                 #include "acpi/routing.asl"
  40
  41                 Device(PWRB) {
  42                         Name(_HID, EISAID("PNP0C0C"))
  43                         Name(_UID, 0xAA)
  44                         Name(_PRW, Package () {3, 0x04})
  45                         Name(_STA, 0x0B)
  46                 }
  47
  48                 Device(PCI0) {
  49                         /* Describe the AMD Northbridge */
  50                         #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
  51
  52                         /* Describe the AMD Fusion Controller Hub Southbridge */
  53                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  54                 }
  55
  56                 /* Describe PCI INT[A-H] for the Southbridge */
  57                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  58
  59         } /* End \_SB scope */
  60
  61         /* Describe SMBUS for the Southbridge */
  62         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  63
  64         /* Define the General Purpose Events for the platform */
  65         #include "acpi/gpe.asl"
  66
  67         /* Define the Thermal zones and methods for the platform */
  68         #include "acpi/thermal.asl"
  69
  70         /* Define the System Indicators for the platform */
  71         #include "acpi/si.asl"
  72 }
  73 /* End of ASL file */