1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* DefinitionBlock Statement */
11 0x00010001 /* OEM Revision */
13 { /* Start of ASL file */
15 /* Globals for the platform */
16 #include "acpi/mainboard.asl"
18 /* Describe the USB Overcurrent pins */
19 #include "acpi/usb_oc.asl"
21 /* PCI IRQ mapping for the Southbridge */
22 #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
24 /* Describe the processor tree (\_SB) */
25 #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
27 /* Describe the supported Sleep States for this Southbridge */
28 #include <southbridge/amd/common/acpi/sleepstates.asl>
30 /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
31 #include "acpi/sleep.asl"
34 /* global utility methods expected within the \_SB scope */
35 #include <arch/x86/acpi/globutil.asl>
37 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
38 #include "acpi/routing.asl"
41 /* Describe the AMD Northbridge */
42 #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
44 /* Describe the AMD Fusion Controller Hub Southbridge */
45 #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
49 /* Describe PCI INT[A-H] for the Southbridge */
50 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
52 } /* End Scope(_SB) */
54 /* Describe SMBUS for the Southbridge */
55 #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
57 /* Define the General Purpose Events for the platform */
58 #include "acpi/gpe.asl"
60 /* Define the Thermal zones and methods for the platform */
61 #include "acpi/thermal.asl"
63 /* Define the System Indicators for the platform */
64 #include "acpi/si.asl"