3 List of upstream coreboot maintainers
4 and how to submit coreboot changes
6 This represents the list of maintainers that work on the upstream coreboot
7 code base (on coreboot.org). Maintainers are assigned to topics and when
8 applicable to subtrees of the source tree. You'll find some subtrees that
9 don't have a maintainer. If you are looking for reviewers for such a sub-
10 tree, it's often a good choice to look at the git history to see who worked
13 Please try to follow the guidelines below. This will make things
14 easier on the maintainers. Not all of these guidelines matter for every
15 trivial patch so apply some common sense.
17 1. Always _test_ your changes, however small, on at least 1 or
18 2 people, preferably many more.
20 2. Try to release a few ALPHA test versions to gerrit. Announce
21 them onto the coreboot mailing list and IRC channel and await
22 results. This is especially important on coreboot core changes,
23 but also for device drivers, because often that's the only way
24 you will find things like the fact revision 3 chipset needs
25 a magic fix you didn't know about, or some clown changed the
26 chips on a board and not its name. (Don't laugh!)
28 3. Make sure your changes compile correctly in multiple
29 configurations. In particular check that changes work for all
30 boards in the tree (use abuild!)
32 4. When you are happy with a change make it generally available for
33 testing in gerrit and await feedback.
35 5. Make your patch available through coreboot's gerrit code review
36 system, and add the relevant maintainer from this list as a code
37 reviewer. Be prepared to get your changes sent back with seemingly
38 silly requests about formatting and variable names. These aren't
39 as silly as they seem. One job the maintainers do is to keep
40 things looking the same. Sometimes this means that the clever
41 hack in your mainboard or chipset to get around a problem actually
42 needs to become a generalized coreboot feature ready for next time.
44 PLEASE check your patch with the automated style checker
45 (util/lint/checkpatch.pl) to catch trival style violations.
46 See https://www.coreboot.org/Coding_Style for guidance here.
48 PLEASE add the maintainers that are generated by
49 util/scripts/get_maintainer.pl as reviewers. The results returned
50 by the script will be best if you have git installed and are
51 making your changes in a branch derived from coreboot.org's latest
54 PLEASE try to include any credit lines you want added with the
55 patch. It avoids people being missed off by mistake and makes
56 it easier to know who wants adding and who doesn't.
58 PLEASE document known bugs. If it doesn't work for everything
59 or does something very odd once a month document it.
61 PLEASE remember that submissions must be made under the terms
62 of the OSDL certificate of contribution and should include a
63 Signed-off-by: line. The current version of this "Developer's
64 Certificate of Origin" (DCO) is listed at
65 https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
67 6. Make sure you have the right to send any changes you make. If you
68 do changes at work you may find your employer owns the patch
73 Descriptions of section entries:
75 M: Maintainer: FullName <address@domain>
76 Must be registered to Gerrit (https://review.coreboot.org/).
77 Should have experience with upstream coreboot development.
78 R: Designated reviewer: FullName <address@domain>
79 These reviewers should be CCed on patches.
80 L: Mailing list that is relevant to this area
81 W: Web-page with status/info
82 Q: Patchwork web based patch tracking system site
83 T: SCM tree type and location.
84 Type is one of: git, hg, quilt, stgit, topgit
85 S: Status, one of the following:
86 Supported: Someone is continuously paid to look after this and
87 a reaction to review requests can be expected
88 within a few days, a month at most.
89 Maintained: Someone actually looks after it and a reaction to
90 review requests can usually be expected within a
92 Odd Fixes: It has a maintainer but they don't have time to do
93 much other than throw the odd patch in. See below..
94 Orphan: No current maintainer [but maybe you could take the
95 role as you write your new code].
96 Obsolete: Old code. Something tagged obsolete generally means
97 it has been replaced by a better system and you
99 F: Files and directories with wildcard patterns.
100 A trailing slash includes all files and subdirectory files.
101 F: drivers/net/ all files in and below drivers/net
102 F: drivers/net/* all files in drivers/net, but not below
103 F: */net/* all files in "any top level directory"/net
104 One pattern per line. Multiple F: lines acceptable.
105 N: Files and directories with regex patterns.
106 N: [^a-z]tegra all files whose path contains the word tegra
107 One pattern per line. Multiple N: lines acceptable.
108 scripts/get_maintainer.pl has different behavior for files that
109 match F: pattern and matches of N: patterns. By default,
110 get_maintainer will not look at git log history when an F: pattern
111 match occurs. When an N: match occurs, git log history is used
112 to also notify the people that have git commit signatures.
113 X: Files and directories that are NOT maintained, same rules as F:
114 Files exclusions are tested before file matches.
115 Can be useful for excluding a specific subdirectory, for instance:
118 matches all files in and below net excluding net/ipv6/
119 K: Keyword perl extended regex pattern to match content in a
120 patch or file. For instance:
122 matches patches or files that contain "of_get_profile"
123 K: \b(printk|pr_(info|err))\b
124 matches patches or files that contain one or more of the words
125 printk, pr_info or pr_err
126 One regex pattern per line. Multiple K: lines acceptable.
128 Note: For the hard of thinking, this list is meant to remain in alphabetical
129 order. If you could add yourselves to it in alphabetical order that would be
132 Maintainers List (try to look for most precise areas first)
134 -----------------------------------
137 M: Ronald Minnich <rminnich@gmail.com>
138 M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
143 F: src/mainboard/emulation/*-riscv/
144 F: src/mainboard/sifive/
148 M: Ronald Minnich <rminnich@gmail.com>
149 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
152 F: src/cpu/qemu-power8/
153 F: src/mainboard/emulation/qemu-power8/
156 M: Alexander Couzens <lynxis@fe80.eu>
161 M: Alexander Couzens <lynxis@fe80.eu>
162 M: Patrick Rudolph <siro@das-labor.org>
164 F: src/mainboard/lenovo/
166 INTEL PINEVIEW CHIPSET
167 M: Damien Zammit <damien@zamaudio.com>
169 F: src/northbridge/intel/pineview/
171 INTEL D510MO MAINBOARD
172 M: Damien Zammit <damien@zamaudio.com>
174 F: src/mainboard/intel/d510mo
177 M: Damien Zammit <damien@zamaudio.com>
179 F: src/northbridge/intel/x4x/
181 GIGABYTE GA-G41M-ES2L MAINBOARD
182 M: Damien Zammit <damien@zamaudio.com>
184 F: src/mainboard/gigabyte/ga-g41m-es2l
186 GOOGLE PANTHER MAINBOARD
187 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
189 F: src/mainboard/google/panther/
191 INTEL MINNOWBOARD MAX MAINBOARD
192 M: Huang Jin <huang.jin@intel.com>
193 M: York Yang <york.yang@intel.com>
195 F: src/mainboard/intel/minnowmax/
197 INTEL FSP BAYTRAIL CHIP & CRBs
198 M: Huang Jin <huang.jin@intel.com>
199 M: York Yang <york.yang@intel.com>
201 F: src/soc/intel/fsp_baytrail/
202 F: src/vendorcode/intel/fsp1_0/baytrail/
203 F: src/mainboard/intel/bakersport_fsp/
204 F: src/mainboard/intel/bayleybay_fsp/
206 INTEL FSP BROADWELL-DE SOC & CRB
207 M: York Yang <york.yang@intel.com>
209 F: src/soc/intel/fsp_broadwell_de/
210 F: src/vendorcode/intel/fsp1_0/broadwell_de/
211 F: src/mainboard/intel/camelbackmountain_fsp/
213 INTEL FSP IVYBRIDGE/PANTHERPOINT/CAVECREEK & CRBs
214 M: York Yang <york.yang@intel.com>
216 F: src/cpu/intel/fsp_model_206ax/
217 F: src/northbridge/intel/fsp_sandybridge/
218 F: src/southbridge/intel/fsp_bd82x6x/
219 F: src/southbridge/intel/fsp_i89xx/
220 F: src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x
221 F: src/vendorcode/intel/fsp1_0/ivybridge_i89xx
222 F: src/mainboard/intel/cougar_canyon2/
223 F: src/mainboard/intel/stargo2/
225 INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
226 M: SweeHeng Wong <swee.heng.wong@intel.com>
227 M: Jeff Daly <jeffrey.daly@intel.com>
228 M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
229 M: David Guckian <david.guckian@intel.com>
230 M: Shine Liu <shine.liu@intel.com>
232 F: src/mainboard/intel/harcuvar/
233 F: src/soc/intel/denverton_ns/
234 F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
236 FSP 1.0 RANGELEY & CRB
237 M: David Guckian <david.guckian@intel.com>
238 M: Fei Wang <fei.z.wang@intel.com>
240 F: src/cpu/intel/fsp_model_406dx/
241 F: src/northbridge/intel/fsp_rangeley/
242 F: src/southbridge/intel/fsp_rangeley/
243 F: src/vendorcode/intel/fsp1_0/rangeley/
244 F: src/mainboard/intel/mohonpeak/
247 M: Huang Jin <huang.jin@intel.com>
248 M: York Yang <york.yang@intel.com>
250 F: src/drivers/intel/fsp1_0/
253 M: Lee Leahy <leroy.p.leahy@intel.com>
254 M: Huang Jin <huang.jin@intel.com>
255 M: York Yang <york.yang@intel.com>
257 F: src/drivers/intel/fsp1_1/
260 M: Andrey Petrov <andrey.petrov@gmail.com>
262 F: src/drivers/intel/fsp2_0/
264 INTEL STRAGO MAINBOARD
265 M: Hannah Williams <hannah.williams@intel.com>
267 F: /src/mainboard/intel/strago/
270 M: Hannah Williams <hannah.williams@intel.com>
272 F: /src/soc/intel/braswell
273 F: /src/vendorcode/intel/fsp/fsp1_1/braswell
276 M: Andrey Petrov <andrey.petrov@gmail.com>
278 F: src/soc/intel/apollolake/
280 ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
281 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
283 F: src/mainboard/asus/kfsn4-dre/
284 F: src/mainboard/asus/kfsn4-dre_k8/
286 ASUS KCMA-D8 MAINBOARD
287 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
289 F: src/mainboard/asus/kcma-d8/
291 ASUS KGPE-D16 MAINBOARD
292 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
294 F: src/mainboard/asus/kgpe-d16/
296 PC ENGINES ALL MAINBOARDS
297 M: Piotr Król <piotr.krol@3mdeb.com>
298 M: Michał Żygowski <michal.zygowski@3mdeb.com>
300 F: src/mainboard/pcengines/
302 AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
303 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
305 F: src/cpu/amd/family_10h-family_15h/
306 F: src/northbridge/amd/amdfam10/
307 F: src/northbridge/amd/amdmct/
308 F: src/northbridge/amd/amdht/
310 AMD SB700 (NON-CIMX) SOUTHBRIDGE
311 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
313 F: src/southbridge/amd/sb700/
315 AMD SR5650 SOUTHBRIDGE
316 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
318 F: src/southbridge/amd/sr5650/
320 ASPEED AST2050 DRIVER & COMMON CODE
321 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
323 F: src/drivers/aspeed/common/
324 F: src/drivers/aspeed/ast2050/
328 F: src/drivers/ati/mach64/
331 M: Patrick Georgi <patrick@georgi-clan.de>
332 M: Martin Roth <gaumless@gmail.com>
338 F: src/arch/x86/acpi/
342 M: Julius Werner <jwerner@chromium.org>
344 F: src/commonlib/lz4*
345 F: payloads/libpayload/liblz4/
346 F: util/cbfstool/lz4/
349 M: Julius Werner <jwerner@chromium.org>
361 F: src/cpu/allwinner/
368 F: util/arm_boot_tools/
384 F: src/include/cpu/x86/
387 M: Patrick Rudolph <siro@das-labor.org>
389 F: src/vendorcode/intel/
391 F: src/northbridge/intel/
392 F: src/southbridge/intel/
394 F: src/drivers/intel/
395 F: src/include/cpu/intel/
398 F: src/vendorcode/amd/
400 F: src/northbridge/amd/
401 F: src/southbridge/amd/
402 F: src/include/cpu/amd/
406 F: src/northbridge/via/
407 F: src/southbridge/via/
410 M: Patrick Georgi <patrick@georgi-clan.de>
411 M: Martin Roth <gaumless@gmail.com>
416 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
420 M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
424 M: Nicola Corna <nicola@corna.info>
425 W: https://github.com/corna/me_cleaner
430 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
434 M: Patrick Georgi <patrick@georgi-clan.de>
435 M: Martin Roth <gaumless@gmail.com>
439 F: src/include/kconfig.h
446 F: util/board_status/
453 F: src/vendorcode/google/chromeos/
455 F: src/include/tpm_lite/
459 F: src/include/device/
460 F: src/include/cpu/cpu.h
462 OPTION ROM EXECUTION & X86EMU
466 F: src/include/cbfs.h
467 F: src/include/cbfs_serialized.h
471 F: src/include/cbmem.h
472 F: src/include/cbmem_id.h
477 F: src/include/console/
483 F: payloads/nvramcui/
486 F: payloads/libpayload/
492 F: payloads/coreinfo/
494 EXTERNAL PAYLOADS INTEGRATION
495 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
496 M: Martin Roth <gaumless@gmail.com>
500 M: Aaron Durbin <adurbin@chromium.org>
501 F: src/vendorcode/google/chromeos/vboot2/
504 M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
505 F: src/drivers/*/tpm/
506 F: src/security/tpm12/
507 F: src/security/tpm20/
508 F: util/tss-generator/
511 M: Martin Roth <gaumless@gmail.com>
522 SUPERIOS & SUPERIOTOOL
523 M: Felix Held <felix-coreboot@felixheld.de>
529 M: Julius Werner <jwerner@chromium.org>
534 MISSING: TIMERS / DELAYS
544 MISSING: DMP / QEMU-X86
551 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
552 T: git https://review.coreboot.org/coreboot
553 S: Buried alive in mainboards
557 # *** Infrastructure Owners***
558 # This is intended to let people know who they should contact for issues with various infrastructure pieces.
560 # Owners: Stefan, Patrick
564 # Owners: Stefan, Patrick
568 # Owners: Martin, Philipp
569 # Backups: Patrick, Stefan
571 # Documentation Website
572 # Owners: Patrick, Philipp
576 # Owners: Stefan, Patrick
580 # Owners: Stefan, Patrick
584 # Owners: Patrick, Martin
592 # Owners: Stefan, Patrick
595 # Software Freedom Conservancy
596 # Main contact: Martin
597 # “Official” contact: Stefan