?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
{drivers,southbridge}: Replace min() with MIN()
[coreboot.git] / src / southbridge / intel / common / spi.c
blob63206d0a831fa371a665fa69d793b887d9bc3f48
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
4 * Copyright (C) 2011 Stefan Tauner
5 * Copyright (C) 2018 Siemens AG
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but without any warranty; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #define __SIMPLE_DEVICE__
19
20 /* This file is derived from the flashrom project. */
21
22 #include <stdint.h>
23 #include <string.h>
24 #include <bootstate.h>
25 #include <commonlib/helpers.h>
26 #include <delay.h>
27 #include <device/mmio.h>
28 #include <device/pci_ops.h>
29 #include <console/console.h>
30 #include <device/device.h>
31 #include <device/pci.h>
32 #include <spi_flash.h>
33 #include <spi-generic.h>
34
35 #include "spi.h"
36
37 #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
38 #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
39 #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
40 #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
41
42 static int spi_is_multichip(void);
43
44 struct ich7_spi_regs {
45 uint16_t spis;
46 uint16_t spic;
47 uint32_t spia;
48 uint64_t spid[8];
49 uint64_t _pad;
50 uint32_t bbar;
51 uint16_t preop;
52 uint16_t optype;
53 uint8_t opmenu[8];
54 uint32_t pbr[3];
55 } __packed;
56
57 struct ich9_spi_regs {
58 uint32_t bfpr;
59 uint16_t hsfs;
60 uint16_t hsfc;
61 uint32_t faddr;
62 uint32_t _reserved0;
63 uint32_t fdata[16];
64 uint32_t frap;
65 uint32_t freg[5];
66 uint32_t _reserved1[3];
67 uint32_t pr[5];
68 uint32_t _reserved2[2];
69 uint8_t ssfs;
70 uint8_t ssfc[3];
71 uint16_t preop;
72 uint16_t optype;
73 uint8_t opmenu[8];
74 uint32_t bbar;
75 uint8_t _reserved3[12];
76 uint32_t fdoc;
77 uint32_t fdod;
78 uint8_t _reserved4[8];
79 uint32_t afc;
80 uint32_t lvscc;
81 uint32_t uvscc;
82 uint8_t _reserved5[4];
83 uint32_t fpb;
84 uint8_t _reserved6[28];
85 uint32_t srdl;
86 uint32_t srdc;
87 uint32_t srd;
88 } __packed;
89
90 struct ich_spi_controller {
91 int locked;
92 uint32_t flmap0;
93 uint32_t flcomp;
94 uint32_t hsfs;
95
96 union {
97 struct ich9_spi_regs *ich9_spi;
98 struct ich7_spi_regs *ich7_spi;
99 };
100 uint8_t *opmenu;
101 int menubytes;
102 uint16_t *preop;
103 uint16_t *optype;
104 uint32_t *addr;
105 uint8_t *data;
106 unsigned int databytes;
107 uint8_t *status;
108 uint16_t *control;
109 uint32_t *bbar;
110 uint32_t *fpr;
111 uint8_t fpr_max;
112 };
113
114 static struct ich_spi_controller cntlr;
115
116 enum {
117 SPIS_SCIP = 0x0001,
118 SPIS_GRANT = 0x0002,
119 SPIS_CDS = 0x0004,
120 SPIS_FCERR = 0x0008,
121 SSFS_AEL = 0x0010,
122 SPIS_LOCK = 0x8000,
123 SPIS_RESERVED_MASK = 0x7ff0,
124 SSFS_RESERVED_MASK = 0x7fe2
125 };
126
127 enum {
128 SPIC_SCGO = 0x000002,
129 SPIC_ACS = 0x000004,
130 SPIC_SPOP = 0x000008,
131 SPIC_DBC = 0x003f00,
132 SPIC_DS = 0x004000,
133 SPIC_SME = 0x008000,
134 SSFC_SCF_MASK = 0x070000,
135 SSFC_RESERVED = 0xf80000
136 };
137
138 enum {
139 HSFS_FDONE = 0x0001,
140 HSFS_FCERR = 0x0002,
141 HSFS_AEL = 0x0004,
142 HSFS_BERASE_MASK = 0x0018,
143 HSFS_BERASE_SHIFT = 3,
144 HSFS_SCIP = 0x0020,
145 HSFS_FDOPSS = 0x2000,
146 HSFS_FDV = 0x4000,
147 HSFS_FLOCKDN = 0x8000
148 };
149
150 enum {
151 HSFC_FGO = 0x0001,
152 HSFC_FCYCLE_MASK = 0x0006,
153 HSFC_FCYCLE_SHIFT = 1,
154 HSFC_FDBC_MASK = 0x3f00,
155 HSFC_FDBC_SHIFT = 8,
156 HSFC_FSMIE = 0x8000
157 };
158
159 enum {
160 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
161 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
162 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
163 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
164 };
165
166 #if CONFIG(DEBUG_SPI_FLASH)
167
168 static u8 readb_(const void *addr)
169 {
170 u8 v = read8(addr);
171
172 printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
173 v, ((unsigned int) addr & 0xffff) - 0xf020);
174 return v;
175 }
176
177 static u16 readw_(const void *addr)
178 {
179 u16 v = read16(addr);
180
181 printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
182 v, ((unsigned int) addr & 0xffff) - 0xf020);
183 return v;
184 }
185
186 static u32 readl_(const void *addr)
187 {
188 u32 v = read32(addr);
189
190 printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
191 v, ((unsigned int) addr & 0xffff) - 0xf020);
192 return v;
193 }
194
195 static void writeb_(u8 b, void *addr)
196 {
197 write8(addr, b);
198 printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
199 b, ((unsigned int) addr & 0xffff) - 0xf020);
200 }
201
202 static void writew_(u16 b, void *addr)
203 {
204 write16(addr, b);
205 printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
206 b, ((unsigned int) addr & 0xffff) - 0xf020);
207 }
208
209 static void writel_(u32 b, void *addr)
210 {
211 write32(addr, b);
212 printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
213 b, ((unsigned int) addr & 0xffff) - 0xf020);
214 }
215
216 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
217
218 #define readb_(a) read8(a)
219 #define readw_(a) read16(a)
220 #define readl_(a) read32(a)
221 #define writeb_(val, addr) write8(addr, val)
222 #define writew_(val, addr) write16(addr, val)
223 #define writel_(val, addr) write32(addr, val)
224
225 #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
226
227 static void write_reg(const void *value, void *dest, uint32_t size)
228 {
229 const uint8_t *bvalue = value;
230 uint8_t *bdest = dest;
231
232 while (size >= 4) {
233 writel_(*(const uint32_t *)bvalue, bdest);
234 bdest += 4; bvalue += 4; size -= 4;
235 }
236 while (size) {
237 writeb_(*bvalue, bdest);
238 bdest++; bvalue++; size--;
239 }
240 }
241
242 static void read_reg(const void *src, void *value, uint32_t size)
243 {
244 const uint8_t *bsrc = src;
245 uint8_t *bvalue = value;
246
247 while (size >= 4) {
248 *(uint32_t *)bvalue = readl_(bsrc);
249 bsrc += 4; bvalue += 4; size -= 4;
250 }
251 while (size) {
252 *bvalue = readb_(bsrc);
253 bsrc++; bvalue++; size--;
254 }
255 }
256
257 static void ich_set_bbar(uint32_t minaddr)
258 {
259 const uint32_t bbar_mask = 0x00ffff00;
260 uint32_t ichspi_bbar;
261
262 minaddr &= bbar_mask;
263 ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
264 ichspi_bbar |= minaddr;
265 writel_(ichspi_bbar, cntlr.bbar);
266 }
267
268 #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
269 #define MENU_BYTES member_size(struct ich7_spi_regs, opmenu)
270 #else
271 #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu)
272 #endif
273
274 #define RCBA 0xf0
275 #define SBASE 0x54
276
277 static void *get_spi_bar(pci_devfn_t dev)
278 {
279 uintptr_t rcba; /* Root Complex Register Block */
280 uintptr_t sbase;
281
282 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
283 rcba = pci_read_config32(dev, RCBA);
284 return (void *)((rcba & 0xffffc000) + 0x3020);
285 }
286 if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) {
287 sbase = pci_read_config32(dev, SBASE);
288 sbase &= ~0x1ff;
289 return (void *)sbase;
290 }
291 if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
292 rcba = pci_read_config32(dev, RCBA);
293 return (void *)((rcba & 0xffffc000) + 0x3800);
294 }
295 }
296
297 void spi_init(void)
298 {
299 uint8_t bios_cntl;
300 struct ich9_spi_regs *ich9_spi;
301 struct ich7_spi_regs *ich7_spi;
302 uint16_t hsfs;
303
304 pci_devfn_t dev = PCI_DEV(0, 31, 0);
305
306 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
307 ich7_spi = get_spi_bar(dev);
308 cntlr.ich7_spi = ich7_spi;
309 cntlr.opmenu = ich7_spi->opmenu;
310 cntlr.menubytes = sizeof(ich7_spi->opmenu);
311 cntlr.optype = &ich7_spi->optype;
312 cntlr.addr = &ich7_spi->spia;
313 cntlr.data = (uint8_t *)ich7_spi->spid;
314 cntlr.databytes = sizeof(ich7_spi->spid);
315 cntlr.status = (uint8_t *)&ich7_spi->spis;
316 cntlr.control = &ich7_spi->spic;
317 cntlr.bbar = &ich7_spi->bbar;
318 cntlr.preop = &ich7_spi->preop;
319 cntlr.fpr = &ich7_spi->pbr[0];
320 cntlr.fpr_max = 3;
321 } else {
322 ich9_spi = get_spi_bar(dev);
323 cntlr.ich9_spi = ich9_spi;
324 hsfs = readw_(&ich9_spi->hsfs);
325 cntlr.hsfs = hsfs;
326 cntlr.opmenu = ich9_spi->opmenu;
327 cntlr.menubytes = sizeof(ich9_spi->opmenu);
328 cntlr.optype = &ich9_spi->optype;
329 cntlr.addr = &ich9_spi->faddr;
330 cntlr.data = (uint8_t *)ich9_spi->fdata;
331 cntlr.databytes = sizeof(ich9_spi->fdata);
332 cntlr.status = &ich9_spi->ssfs;
333 cntlr.control = (uint16_t *)ich9_spi->ssfc;
334 cntlr.bbar = &ich9_spi->bbar;
335 cntlr.preop = &ich9_spi->preop;
336 cntlr.fpr = &ich9_spi->pr[0];
337 cntlr.fpr_max = 5;
338
339 if (cntlr.hsfs & HSFS_FDV) {
340 writel_(4, &ich9_spi->fdoc);
341 cntlr.flmap0 = readl_(&ich9_spi->fdod);
342 writel_(0x1000, &ich9_spi->fdoc);
343 cntlr.flcomp = readl_(&ich9_spi->fdod);
344 }
345 }
346
347 ich_set_bbar(0);
348
349 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
350 /* Disable the BIOS write protect so write commands are allowed. */
351 bios_cntl = pci_read_config8(dev, 0xdc);
352 /* Deassert SMM BIOS Write Protect Disable. */
353 bios_cntl &= ~(1 << 5);
354 pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
355 }
356 }
357
358 static int spi_locked(void)
359 {
360 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
361 return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
362 } else {
363 return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
364 }
365 }
366
367 static void spi_init_cb(void *unused)
368 {
369 spi_init();
370 }
371
372 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
373
374 typedef struct spi_transaction {
375 const uint8_t *out;
376 uint32_t bytesout;
377 uint8_t *in;
378 uint32_t bytesin;
379 uint8_t type;
380 uint8_t opcode;
381 uint32_t offset;
382 } spi_transaction;
383
384 static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
385 {
386 trans->out += bytes;
387 trans->bytesout -= bytes;
388 }
389
390 static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
391 {
392 trans->in += bytes;
393 trans->bytesin -= bytes;
394 }
395
396 static void spi_setup_type(spi_transaction *trans)
397 {
398 trans->type = 0xFF;
399
400 /* Try to guess spi type from read/write sizes. */
401 if (trans->bytesin == 0) {
402 if (trans->bytesout > 4)
403 /*
404 * If bytesin = 0 and bytesout > 4, we presume this is
405 * a write data operation, which is accompanied by an
406 * address.
407 */
408 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
409 else
410 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
411 return;
412 }
413
414 if (trans->bytesout == 1) { /* and bytesin is > 0 */
415 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
416 return;
417 }
418
419 if (trans->bytesout == 4) { /* and bytesin is > 0 */
420 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
421 }
422
423 /* Fast read command is called with 5 bytes instead of 4 */
424 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
425 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
426 --trans->bytesout;
427 }
428 }
429
430 static int spi_setup_opcode(spi_transaction *trans)
431 {
432 uint16_t optypes;
433 uint8_t opmenu[MENU_BYTES];
434
435 trans->opcode = trans->out[0];
436 spi_use_out(trans, 1);
437 if (!spi_locked()) {
438 /* The lock is off, so just use index 0. */
439 writeb_(trans->opcode, cntlr.opmenu);
440 optypes = readw_(cntlr.optype);
441 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
442 writew_(optypes, cntlr.optype);
443 return 0;
444 }
445
446 /* The lock is on. See if what we need is on the menu. */
447 uint8_t optype;
448 uint16_t opcode_index;
449
450 /* Write Enable is handled as atomic prefix */
451 if (trans->opcode == SPI_OPCODE_WREN)
452 return 0;
453
454 read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
455 for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
456 if (opmenu[opcode_index] == trans->opcode)
457 break;
458 }
459
460 if (opcode_index == ARRAY_SIZE(opmenu)) {
461 printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
462 trans->opcode);
463 return -1;
464 }
465
466 optypes = readw_(cntlr.optype);
467 optype = (optypes >> (opcode_index * 2)) & 0x3;
468 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
469 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
470 trans->bytesout >= 3) {
471 /* We guessed wrong earlier. Fix it up. */
472 trans->type = optype;
473 }
474 if (optype != trans->type) {
475 printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
476 optype);
477 return -1;
478 }
479 return opcode_index;
480 }
481
482 static int spi_setup_offset(spi_transaction *trans)
483 {
484 /* Separate the SPI address and data. */
485 switch (trans->type) {
486 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
487 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
488 return 0;
489 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
490 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
491 trans->offset = ((uint32_t)trans->out[0] << 16) |
492 ((uint32_t)trans->out[1] << 8) |
493 ((uint32_t)trans->out[2] << 0);
494 spi_use_out(trans, 3);
495 return 1;
496 default:
497 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
498 return -1;
499 }
500 }
501
502 /*
503 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
504 * below is True) or 0. In case the wait was for the bit(s) to set - write
505 * those bits back, which would cause resetting them.
506 *
507 * Return the last read status value on success or -1 on failure.
508 */
509 static int ich_status_poll(u16 bitmask, int wait_til_set)
510 {
511 int timeout = 600000; /* This will result in 6 seconds */
512 u16 status = 0;
513
514 while (timeout--) {
515 status = readw_(cntlr.status);
516 if (wait_til_set ^ ((status & bitmask) == 0)) {
517 if (wait_til_set)
518 writew_((status & bitmask), cntlr.status);
519 return status;
520 }
521 udelay(10);
522 }
523
524 printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n",
525 status, bitmask);
526 return -1;
527 }
528
529 static int spi_is_multichip(void)
530 {
531 if (!(cntlr.hsfs & HSFS_FDV))
532 return 0;
533 return !!((cntlr.flmap0 >> 8) & 3);
534 }
535
536 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
537 size_t bytesout, void *din, size_t bytesin)
538 {
539 uint16_t control;
540 int16_t opcode_index;
541 int with_address;
542 int status;
543
544 spi_transaction trans = {
545 dout, bytesout,
546 din, bytesin,
547 0xff, 0xff, 0
548 };
549
550 /* There has to always at least be an opcode. */
551 if (!bytesout || !dout) {
552 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
553 return -1;
554 }
555 /* Make sure if we read something we have a place to put it. */
556 if (bytesin != 0 && !din) {
557 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
558 return -1;
559 }
560
561 if (ich_status_poll(SPIS_SCIP, 0) == -1)
562 return -1;
563
564 writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
565
566 spi_setup_type(&trans);
567 if ((opcode_index = spi_setup_opcode(&trans)) < 0)
568 return -1;
569 if ((with_address = spi_setup_offset(&trans)) < 0)
570 return -1;
571
572 if (trans.opcode == SPI_OPCODE_WREN) {
573 /*
574 * Treat Write Enable as Atomic Pre-Op if possible
575 * in order to prevent the Management Engine from
576 * issuing a transaction between WREN and DATA.
577 */
578 if (!spi_locked())
579 writew_(trans.opcode, cntlr.preop);
580 return 0;
581 }
582
583 /* Preset control fields */
584 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
585
586 /* Issue atomic preop cycle if needed */
587 if (readw_(cntlr.preop))
588 control |= SPIC_ACS;
589
590 if (!trans.bytesout && !trans.bytesin) {
591 /* SPI addresses are 24 bit only */
592 if (with_address)
593 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
594
595 /*
596 * This is a 'no data' command (like Write Enable), its
597 * bitesout size was 1, decremented to zero while executing
598 * spi_setup_opcode() above. Tell the chip to send the
599 * command.
600 */
601 writew_(control, cntlr.control);
602
603 /* wait for the result */
604 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
605 if (status == -1)
606 return -1;
607
608 if (status & SPIS_FCERR) {
609 printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
610 return -1;
611 }
612
613 goto spi_xfer_exit;
614 }
615
616 /*
617 * Check if this is a write command attempting to transfer more bytes
618 * than the controller can handle. Iterations for writes are not
619 * supported here because each SPI write command needs to be preceded
620 * and followed by other SPI commands, and this sequence is controlled
621 * by the SPI chip driver.
622 */
623 if (trans.bytesout > cntlr.databytes) {
624 printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
625 " spi_crop_chunk()?\n");
626 return -1;
627 }
628
629 /*
630 * Read or write up to databytes bytes at a time until everything has
631 * been sent.
632 */
633 while (trans.bytesout || trans.bytesin) {
634 uint32_t data_length;
635
636 /* SPI addresses are 24 bit only */
637 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
638
639 if (trans.bytesout)
640 data_length = MIN(trans.bytesout, cntlr.databytes);
641 else
642 data_length = MIN(trans.bytesin, cntlr.databytes);
643
644 /* Program data into FDATA0 to N */
645 if (trans.bytesout) {
646 write_reg(trans.out, cntlr.data, data_length);
647 spi_use_out(&trans, data_length);
648 if (with_address)
649 trans.offset += data_length;
650 }
651
652 /* Add proper control fields' values */
653 control &= ~((cntlr.databytes - 1) << 8);
654 control |= SPIC_DS;
655 control |= (data_length - 1) << 8;
656
657 /* write it */
658 writew_(control, cntlr.control);
659
660 /* Wait for Cycle Done Status or Flash Cycle Error. */
661 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
662 if (status == -1)
663 return -1;
664
665 if (status & SPIS_FCERR) {
666 printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
667 return -1;
668 }
669
670 if (trans.bytesin) {
671 read_reg(cntlr.data, trans.in, data_length);
672 spi_use_in(&trans, data_length);
673 if (with_address)
674 trans.offset += data_length;
675 }
676 }
677
678 spi_xfer_exit:
679 /* Clear atomic preop now that xfer is done */
680 writew_(0, cntlr.preop);
681
682 return 0;
683 }
684
685 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
686 static void ich_hwseq_set_addr(uint32_t addr)
687 {
688 uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
689
690 writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
691 }
692
693 /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
694 Resets all error flags in HSFS.
695 Returns 0 if the cycle completes successfully without errors within
696 timeout us, 1 on errors. */
697 static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
698 unsigned int len)
699 {
700 uint16_t hsfs;
701 uint32_t addr;
702
703 timeout /= 8; /* scale timeout duration to counter */
704 while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) &
705 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
706 --timeout) {
707 udelay(8);
708 }
709 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
710
711 if (!timeout) {
712 uint16_t hsfc;
713 addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
714 hsfc = readw_(&cntlr.ich9_spi->hsfc);
715 printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
716 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
717 addr, addr + len - 1, addr, len - 1,
718 hsfc, hsfs);
719 return 1;
720 }
721
722 if (hsfs & HSFS_FCERR) {
723 uint16_t hsfc;
724 addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
725 hsfc = readw_(&cntlr.ich9_spi->hsfc);
726 printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
727 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
728 addr, addr + len - 1, addr, len - 1,
729 hsfc, hsfs);
730 return 1;
731 }
732 return 0;
733 }
734
735
736 static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
737 size_t len)
738 {
739 u32 start, end, erase_size;
740 int ret;
741 uint16_t hsfc;
742 unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS;
743
744 erase_size = flash->sector_size;
745 if (offset % erase_size || len % erase_size) {
746 printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
747 return -1;
748 }
749
750 ret = spi_claim_bus(&flash->spi);
751 if (ret) {
752 printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
753 return ret;
754 }
755
756 start = offset;
757 end = start + len;
758
759 while (offset < end) {
760 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
761 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
762
763 ich_hwseq_set_addr(offset);
764
765 offset += erase_size;
766
767 hsfc = readw_(&cntlr.ich9_spi->hsfc);
768 hsfc &= ~HSFC_FCYCLE; /* clear operation */
769 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
770 hsfc |= HSFC_FGO; /* start */
771 writew_(hsfc, &cntlr.ich9_spi->hsfc);
772 if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
773 printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
774 ret = -1;
775 goto out;
776 }
777 }
778
779 printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
780
781 out:
782 spi_release_bus(&flash->spi);
783 return ret;
784 }
785
786 static void ich_read_data(uint8_t *data, int len)
787 {
788 int i;
789 uint32_t temp32 = 0;
790
791 for (i = 0; i < len; i++) {
792 if ((i % 4) == 0)
793 temp32 = readl_(cntlr.data + i);
794
795 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
796 }
797 }
798
799 static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
800 void *buf)
801 {
802 uint16_t hsfc;
803 uint16_t timeout = 100 * 60;
804 uint8_t block_len;
805
806 if (addr + len > flash->size) {
807 printk(BIOS_ERR,
808 "Attempt to read %x-%x which is out of chip\n",
809 (unsigned int) addr,
810 (unsigned int) addr+(unsigned int) len);
811 return -1;
812 }
813
814 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
815 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
816
817 while (len > 0) {
818 block_len = MIN(len, cntlr.databytes);
819 if (block_len > (~addr & 0xff))
820 block_len = (~addr & 0xff) + 1;
821 ich_hwseq_set_addr(addr);
822 hsfc = readw_(&cntlr.ich9_spi->hsfc);
823 hsfc &= ~HSFC_FCYCLE; /* set read operation */
824 hsfc &= ~HSFC_FDBC; /* clear byte count */
825 /* set byte count */
826 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
827 hsfc |= HSFC_FGO; /* start */
828 writew_(hsfc, &cntlr.ich9_spi->hsfc);
829
830 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
831 return 1;
832 ich_read_data(buf, block_len);
833 addr += block_len;
834 buf += block_len;
835 len -= block_len;
836 }
837 return 0;
838 }
839
840 /* Fill len bytes from the data array into the fdata/spid registers.
841 *
842 * Note that using len > flash->pgm->spi.max_data_write will trash the registers
843 * following the data registers.
844 */
845 static void ich_fill_data(const uint8_t *data, int len)
846 {
847 uint32_t temp32 = 0;
848 int i;
849
850 if (len <= 0)
851 return;
852
853 for (i = 0; i < len; i++) {
854 if ((i % 4) == 0)
855 temp32 = 0;
856
857 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
858
859 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
860 writel_(temp32, cntlr.data + (i - (i % 4)));
861 }
862 i--;
863 if ((i % 4) != 3) /* Write remaining data to regs. */
864 writel_(temp32, cntlr.data + (i - (i % 4)));
865 }
866
867 static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
868 const void *buf)
869 {
870 uint16_t hsfc;
871 uint16_t timeout = 100 * 60;
872 uint8_t block_len;
873 uint32_t start = addr;
874
875 if (addr + len > flash->size) {
876 printk(BIOS_ERR,
877 "Attempt to write 0x%x-0x%x which is out of chip\n",
878 (unsigned int)addr, (unsigned int) (addr+len));
879 return -1;
880 }
881
882 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
883 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
884
885 while (len > 0) {
886 block_len = MIN(len, cntlr.databytes);
887 if (block_len > (~addr & 0xff))
888 block_len = (~addr & 0xff) + 1;
889
890 ich_hwseq_set_addr(addr);
891
892 ich_fill_data(buf, block_len);
893 hsfc = readw_(&cntlr.ich9_spi->hsfc);
894 hsfc &= ~HSFC_FCYCLE; /* clear operation */
895 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
896 hsfc &= ~HSFC_FDBC; /* clear byte count */
897 /* set byte count */
898 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
899 hsfc |= HSFC_FGO; /* start */
900 writew_(hsfc, &cntlr.ich9_spi->hsfc);
901
902 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
903 printk(BIOS_ERR, "SF: write failure at %x\n",
904 addr);
905 return -1;
906 }
907 addr += block_len;
908 buf += block_len;
909 len -= block_len;
910 }
911 printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
912 (unsigned int) (addr - start), start);
913 return 0;
914 }
915
916 static const struct spi_flash_ops spi_flash_ops = {
917 .read = ich_hwseq_read,
918 .write = ich_hwseq_write,
919 .erase = ich_hwseq_erase,
920 };
921
922 static int spi_flash_programmer_probe(const struct spi_slave *spi,
923 struct spi_flash *flash)
924 {
925
926 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
927 return spi_flash_generic_probe(spi, flash);
928
929 /* Try generic probing first if spi_is_multichip returns 0. */
930 if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash))
931 return 0;
932
933 memcpy(&flash->spi, spi, sizeof(*spi));
934 flash->name = "Opaque HW-sequencing";
935
936 ich_hwseq_set_addr(0);
937 switch ((cntlr.hsfs >> 3) & 3) {
938 case 0:
939 flash->sector_size = 256;
940 break;
941 case 1:
942 flash->sector_size = 4096;
943 break;
944 case 2:
945 flash->sector_size = 8192;
946 break;
947 case 3:
948 flash->sector_size = 65536;
949 break;
950 }
951
952 flash->size = 1 << (19 + (cntlr.flcomp & 7));
953
954 flash->ops = &spi_flash_ops;
955
956 if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
957 flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7));
958 printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
959
960 return 0;
961 }
962
963 static int xfer_vectors(const struct spi_slave *slave,
964 struct spi_op vectors[], size_t count)
965 {
966 return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
967 }
968
969 #define SPI_FPR_SHIFT 12
970 #define ICH7_SPI_FPR_MASK 0xfff
971 #define ICH9_SPI_FPR_MASK 0x1fff
972 #define SPI_FPR_BASE_SHIFT 0
973 #define ICH7_SPI_FPR_LIMIT_SHIFT 12
974 #define ICH9_SPI_FPR_LIMIT_SHIFT 16
975 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */
976 #define SPI_FPR_WPE (1 << 31) /* Write Protect */
977
978 static u32 spi_fpr(u32 base, u32 limit)
979 {
980 u32 ret;
981 u32 mask, limit_shift;
982
983 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
984 mask = ICH7_SPI_FPR_MASK;
985 limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT;
986 } else {
987 mask = ICH9_SPI_FPR_MASK;
988 limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT;
989 }
990 ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift;
991 ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT;
992 return ret;
993 }
994
995 /*
996 * Protect range of SPI flash defined by [start, start+size-1] using Flash
997 * Protected Range (FPR) register if available.
998 * Returns 0 on success, -1 on failure of programming fpr registers.
999 */
1000 static int spi_flash_protect(const struct spi_flash *flash,
1001 const struct region *region,
1002 const enum ctrlr_prot_type type)
1003 {
1004 u32 start = region_offset(region);
1005 u32 end = start + region_sz(region) - 1;
1006 u32 reg;
1007 u32 protect_mask = 0;
1008 int fpr;
1009 uint32_t *fpr_base;
1010
1011 fpr_base = cntlr.fpr;
1012
1013 /* Find first empty FPR */
1014 for (fpr = 0; fpr < cntlr.fpr_max; fpr++) {
1015 reg = read32(&fpr_base[fpr]);
1016 if (reg == 0)
1017 break;
1018 }
1019
1020 if (fpr == cntlr.fpr_max) {
1021 printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
1022 return -1;
1023 }
1024
1025 switch (type) {
1026 case WRITE_PROTECT:
1027 protect_mask |= SPI_FPR_WPE;
1028 break;
1029 case READ_PROTECT:
1030 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1031 return -1;
1032 protect_mask |= ICH9_SPI_FPR_RPE;
1033 break;
1034 case READ_WRITE_PROTECT:
1035 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1036 return -1;
1037 protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE);
1038 break;
1039 default:
1040 printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n");
1041 return -1;
1042 }
1043
1044 /* Set protected range base and limit */
1045 reg = spi_fpr(start, end) | protect_mask;
1046
1047 /* Set the FPR register and verify it is protected */
1048 write32(&fpr_base[fpr], reg);
1049 if (reg != read32(&fpr_base[fpr])) {
1050 printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
1051 return -1;
1052 }
1053
1054 printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n",
1055 __func__, fpr, start, end);
1056 return 0;
1057 }
1058
1059 void spi_finalize_ops(void)
1060 {
1061 u16 spi_opprefix;
1062 u16 optype = 0;
1063 struct intel_swseq_spi_config spi_config_default = {
1064 {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
1065 { /* OPCODE and OPTYPE */
1066 {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
1067 {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
1068 {0x03, READ_WITH_ADDR}, /* READ: Read Data */
1069 {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
1070 {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
1071 {0x9f, READ_NO_ADDR}, /* RDID: Read ID */
1072 {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */
1073 {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */
1074 }
1075 };
1076 struct intel_swseq_spi_config spi_config_aai_write = {
1077 {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
1078 { /* OPCODE and OPTYPE */
1079 {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
1080 {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
1081 {0x03, READ_WITH_ADDR}, /* READ: Read Data */
1082 {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
1083 {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
1084 {0x9f, READ_NO_ADDR}, /* RDID: Read ID */
1085 {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */
1086 {0x04, WRITE_NO_ADDR} /* Write Disable */
1087 }
1088 };
1089 const struct spi_flash *flash = boot_device_spi_flash();
1090 struct intel_swseq_spi_config *spi_config = &spi_config_default;
1091 int i;
1092
1093 /*
1094 * Some older SST SPI flashes support AAI write but use 0xaf opcde for
1095 * that. Flashrom uses the byte program opcode to write those flashes,
1096 * so this configuration is fine too. SST25VF064C (id = 0x4b) is an
1097 * exception.
1098 */
1099 if (flash && flash->vendor == VENDOR_ID_SST && (flash->model & 0x00ff) != 0x4b)
1100 spi_config = &spi_config_aai_write;
1101
1102 if (spi_locked())
1103 return;
1104
1105 intel_southbridge_override_spi(spi_config);
1106
1107 spi_opprefix = spi_config->opprefixes[0]
1108 | (spi_config->opprefixes[1] << 8);
1109 writew_(spi_opprefix, cntlr.preop);
1110 for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) {
1111 optype |= (spi_config->ops[i].type & 3) << (i * 2);
1112 writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]);
1113 }
1114 writew_(optype, cntlr.optype);
1115 }
1116
1117 __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
1118 {
1119 }
1120
1121 static const struct spi_ctrlr spi_ctrlr = {
1122 .xfer_vector = xfer_vectors,
1123 .max_xfer_size = member_size(struct ich9_spi_regs, fdata),
1124 .flash_probe = spi_flash_programmer_probe,
1125 .flash_protect = spi_flash_protect,
1126 };
1127
1128 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
1129 {
1130 .ctrlr = &spi_ctrlr,
1131 .bus_start = 0,
1132 .bus_end = 0,
1133 },
1134 };
1135
1136 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
ast, secure and flexible OpenSource firmware