src/mainboard/google/hatch/variants/kohaku/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2019 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/acpi.h>
  17 #include <baseboard/gpio.h>
  18 #include <baseboard/variants.h>
  19 #include <commonlib/helpers.h>
  20
  21 static const struct pad_config gpio_table[] = {
  22         /* A0  : RCIN# ==> NC */
  23         PAD_NC(GPP_A0, NONE),
  24         /* A6  : SERIRQ ==> NC */
  25         PAD_NC(GPP_A6, NONE),
  26         /* A10 : PEN_RESET_ODL for old revision devices */
  27         PAD_CFG_GPO(GPP_A10, 1, DEEP),
  28         /* A16 : EMR_GARAGE_DET (notification) */
  29         PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST),
  30         /* A17 : PIRQA# ==> NC */
  31         PAD_NC(GPP_A17, NONE),
  32         /* A18 : ISH_GP0 ==> NC */
  33         PAD_NC(GPP_A18, NONE),
  34         /* A19 : PEN_RESET_ODL */
  35         PAD_CFG_GPO(GPP_A19, 0, DEEP),
  36         /* A20 : ISH_GP2 ==> NC */
  37         PAD_NC(GPP_A20, NONE),
  38         /* A22 : ISH_GP4 ==> NC */
  39         PAD_NC(GPP_A22, NONE),
  40         /* B8  : SRCCLKREQ3#: NC  */
  41         PAD_NC(GPP_B8, NONE),
  42         /* C1  : SMBDATA: NC  */
  43         PAD_NC(GPP_C1, NONE),
  44         /* C7  : PEN_IRQ_OD_L */
  45         PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
  46         /* C12 : EN_PP3300_TSP_DX */
  47         PAD_CFG_GPO(GPP_C12, 0, DEEP),
  48         /* C15 : EN_PP3300_DIG_DX */
  49         PAD_CFG_GPO(GPP_C15, 0, DEEP),
  50         /* C23 : UART2_CTS# ==> NC */
  51         PAD_NC(GPP_C23, NONE),
  52         /* D16 : TOUCHSCREEN_INT_L */
  53         PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
  54         /* E23 : GPP_E23 ==> NC */
  55         PAD_NC(GPP_E23, NONE),
  56         /* F1 : GPP_F1 ==> NC */
  57         PAD_NC(GPP_F1, NONE),
  58         /* G0 : GPP_G0 ==> NC  */
  59         PAD_NC(GPP_G0, NONE),
  60         /* G1 : GPP_G1 ==> NC  */
  61         PAD_NC(GPP_G1, NONE),
  62         /* G2 : GPP_G2 ==> NC  */
  63         PAD_NC(GPP_G2, NONE),
  64         /* G3 : GPP_G3 ==> NC  */
  65         PAD_NC(GPP_G3, NONE),
  66         /* G4 : GPP_G4 ==> NC  */
  67         PAD_NC(GPP_G4, NONE),
  68         /* G5 : GPP_G5 ==> NC  */
  69         PAD_NC(GPP_G5, NONE),
  70         /* G6 : GPP_G6 ==> NC  */
  71         PAD_NC(GPP_G6, NONE),
  72         /* H4  : PCH_I2C_PEN_SDA */
  73         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  74         /* H5  : PCH_I2C_PEN_SCL */
  75         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  76 };
  77
  78 const struct pad_config *override_gpio_table(size_t *num)
  79 {
  80         *num = ARRAY_SIZE(gpio_table);
  81         return gpio_table;
  82 }
  83
  84 /*
  85  * GPIOs configured before ramstage
  86  * Note: the Hatch platform's romstage will configure
  87  * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
  88  * as inputs before it reads them, so they are not
  89  * needed in this table.
  90  */
  91 static const struct pad_config early_gpio_table[] = {
  92         /* A12 : FPMCU_RST_ODL */
  93         PAD_CFG_GPO(GPP_A12, 0, DEEP),
  94         /* B15 : H1_SLAVE_SPI_CS_L */
  95         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  96         /* B16 : H1_SLAVE_SPI_CLK */
  97         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
  98         /* B17 : H1_SLAVE_SPI_MISO_R */
  99         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 100         /* B18 : H1_SLAVE_SPI_MOSI_R */
 101         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 102         /* C14 : BT_DISABLE_L */
 103         PAD_CFG_GPO(GPP_C14, 0, DEEP),
 104         /* PCH_WP_OD */
 105         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 106         /* C21 : H1_PCH_INT_ODL */
 107         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 108         /* E1  : M2_SSD_PEDET */
 109         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 110         /* E5  : SATA_DEVSLP1 */
 111         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 112         /* F2  : MEM_CH_SEL */
 113         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 114 };
 115
 116 const struct pad_config *variant_early_gpio_table(size_t *num)
 117 {
 118         *num = ARRAY_SIZE(early_gpio_table);
 119         return early_gpio_table;
 120 }
 121
 122 /*
 123  * GPIO settings before entering all sleep states
 124  */
 125 static const struct pad_config sleep_gpio_table[] = {
 126         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 127 };
 128
 129 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 130 {
 131         *num = ARRAY_SIZE(sleep_gpio_table);
 132         return sleep_gpio_table;
 133 }