| blob | 3059be9a37b10c38ab2bbb01b455c887c87508a6 |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 #include <arch/acpi.h>
18 DefinitionBlock (
19 "DSDT.AML", /* Output filename */
20 "DSDT", /* Signature */
21 0x02, /* DSDT Revision, needs to be 2 for 64bit */
22 OEM_ID,
23 ACPI_TABLE_CREATOR,
24 0x00010001 /* OEM Revision */
25 )
26 { /* Start of ASL file */
27 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
29 /* Data to be patched by the BIOS during POST */
30 /* FIXME the patching is not done yet! */
31 /* Memory related values */
32 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
33 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
34 Name(PBLN, 0x0) /* Length of BIOS area */
36 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
37 Name(HPBA, 0xFED00000) /* Base address of HPET table */
39 /* USB overcurrent mapping pins. */
40 Name(UOM0, 0)
41 Name(UOM1, 2)
42 Name(UOM2, 0)
43 Name(UOM3, 7)
44 Name(UOM4, 2)
45 Name(UOM5, 2)
46 Name(UOM6, 6)
47 Name(UOM7, 2)
48 Name(UOM8, 6)
49 Name(UOM9, 6)
51 /* Some global data */
52 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
53 Name(OSV, Ones) /* Assume nothing */
54 Name(PMOD, One) /* Assume APIC */
56 /*
57 * Processor Object
58 *
59 */
60 Scope (\_PR) { /* define processor scope */
61 Processor(
62 CPU0, /* name space name */
63 0, /* Unique number for this processor */
64 0x808, /* PBLK system I/O address !hardcoded! */
65 0x06 /* PBLKLEN for boot processor */
66 ) {
67 #include "acpi/cpstate.asl"
68 }
70 Processor(
71 CPU1, /* name space name */
72 1, /* Unique number for this processor */
73 0x0000, /* PBLK system I/O address !hardcoded! */
74 0x00 /* PBLKLEN for boot processor */
75 ) {
76 #include "acpi/cpstate.asl"
77 }
79 Processor(
80 CPU2, /* name space name */
81 2, /* Unique number for this processor */
82 0x0000, /* PBLK system I/O address !hardcoded! */
83 0x00 /* PBLKLEN for boot processor */
84 ) {
85 #include "acpi/cpstate.asl"
86 }
88 Processor(
89 CPU3, /* name space name */
90 3, /* Unique number for this processor */
91 0x0000, /* PBLK system I/O address !hardcoded! */
92 0x00 /* PBLKLEN for boot processor */
93 ) {
94 #include "acpi/cpstate.asl"
95 }
96 } /* End _PR scope */
98 /* PIC IRQ mapping registers, C00h-C01h */
99 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
100 Field(PRQM, ByteAcc, NoLock, Preserve) {
101 PRQI, 0x00000008,
102 PRQD, 0x00000008, /* Offset: 1h */
103 }
104 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
105 PINA, 0x00000008, /* Index 0 */
106 PINB, 0x00000008, /* Index 1 */
107 PINC, 0x00000008, /* Index 2 */
108 PIND, 0x00000008, /* Index 3 */
109 AINT, 0x00000008, /* Index 4 */
110 SINT, 0x00000008, /* Index 5 */
111 , 0x00000008, /* Index 6 */
112 AAUD, 0x00000008, /* Index 7 */
113 AMOD, 0x00000008, /* Index 8 */
114 PINE, 0x00000008, /* Index 9 */
115 PINF, 0x00000008, /* Index A */
116 PING, 0x00000008, /* Index B */
117 PINH, 0x00000008, /* Index C */
118 }
120 /* PCI Error control register */
121 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
122 Field(PERC, ByteAcc, NoLock, Preserve) {
123 SENS, 0x00000001,
124 PENS, 0x00000001,
125 SENE, 0x00000001,
126 PENE, 0x00000001,
127 }
129 /* Client Management index/data registers */
130 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
131 Field(CMT, ByteAcc, NoLock, Preserve) {
132 CMTI, 8,
133 /* Client Management Data register */
134 G64E, 1,
135 G64O, 1,
136 G32O, 2,
137 , 2,
138 GPSL, 2,
139 }
141 /* GPM Port register */
142 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
143 Field(GPT, ByteAcc, NoLock, Preserve) {
144 GPB0,1,
145 GPB1,1,
146 GPB2,1,
147 GPB3,1,
148 GPB4,1,
149 GPB5,1,
150 GPB6,1,
151 GPB7,1,
152 }
154 /* Flash ROM program enable register */
155 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
156 Field(FRE, ByteAcc, NoLock, Preserve) {
157 , 0x00000006,
158 FLRE, 0x00000001,
159 }
161 /* PM2 index/data registers */
162 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
163 Field(PM2R, ByteAcc, NoLock, Preserve) {
164 PM2I, 0x00000008,
165 PM2D, 0x00000008,
166 }
168 /* Power Management I/O registers */
169 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
170 Field(PIOR, ByteAcc, NoLock, Preserve) {
171 PIOI, 0x00000008,
172 PIOD, 0x00000008,
173 }
174 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
175 Offset(0x00), /* MiscControl */
176 , 1,
177 T1EE, 1,
178 T2EE, 1,
179 Offset(0x01), /* MiscStatus */
180 , 1,
181 T1E, 1,
182 T2E, 1,
183 Offset(0x04), /* SmiWakeUpEventEnable3 */
184 , 7,
185 SSEN, 1,
186 Offset(0x07), /* SmiWakeUpEventStatus3 */
187 , 7,
188 CSSM, 1,
189 Offset(0x10), /* AcpiEnable */
190 , 6,
191 PWDE, 1,
192 Offset(0x1C), /* ProgramIoEnable */
193 , 3,
194 MKME, 1,
195 IO3E, 1,
196 IO2E, 1,
197 IO1E, 1,
198 IO0E, 1,
199 Offset(0x1D), /* IOMonitorStatus */
200 , 3,
201 MKMS, 1,
202 IO3S, 1,
203 IO2S, 1,
204 IO1S, 1,
205 IO0S,1,
206 Offset(0x20), /* AcpiPmEvtBlk */
207 APEB, 16,
208 Offset(0x36), /* GEvtLevelConfig */
209 , 6,
210 ELC6, 1,
211 ELC7, 1,
212 Offset(0x37), /* GPMLevelConfig0 */
213 , 3,
214 PLC0, 1,
215 PLC1, 1,
216 PLC2, 1,
217 PLC3, 1,
218 PLC8, 1,
219 Offset(0x38), /* GPMLevelConfig1 */
220 , 1,
221 PLC4, 1,
222 PLC5, 1,
223 , 1,
224 PLC6, 1,
225 PLC7, 1,
226 Offset(0x3B), /* PMEStatus1 */
227 GP0S, 1,
228 GM4S, 1,
229 GM5S, 1,
230 APS, 1,
231 GM6S, 1,
232 GM7S, 1,
233 GP2S, 1,
234 STSS, 1,
235 Offset(0x55), /* SoftPciRst */
236 SPRE, 1,
237 , 1,
238 , 1,
239 PNAT, 1,
240 PWMK, 1,
241 PWNS, 1,
243 /* Offset(0x61), */ /* Options_1 */
244 /* ,7, */
245 /* R617,1, */
247 Offset(0x65), /* UsbPMControl */
248 , 4,
249 URRE, 1,
250 Offset(0x68), /* MiscEnable68 */
251 , 3,
252 TMTE, 1,
253 , 1,
254 Offset(0x92), /* GEVENTIN */
255 , 7,
256 E7IS, 1,
257 Offset(0x96), /* GPM98IN */
258 G8IS, 1,
259 G9IS, 1,
260 Offset(0x9A), /* EnhanceControl */
261 ,7,
262 HPDE, 1,
263 Offset(0xA8), /* PIO7654Enable */
264 IO4E, 1,
265 IO5E, 1,
266 IO6E, 1,
267 IO7E, 1,
268 Offset(0xA9), /* PIO7654Status */
269 IO4S, 1,
270 IO5S, 1,
271 IO6S, 1,
272 IO7S, 1,
273 }
275 /* PM1 Event Block
276 * First word is PM1_Status, Second word is PM1_Enable
277 */
278 OperationRegion(P1EB, SystemIO, APEB, 0x04)
279 Field(P1EB, ByteAcc, NoLock, Preserve) {
280 TMST, 1,
281 , 3,
282 BMST, 1,
283 GBST, 1,
284 Offset(0x01),
285 PBST, 1,
286 , 1,
287 RTST, 1,
288 , 3,
289 PWST, 1,
290 SPWS, 1,
291 Offset(0x02),
292 TMEN, 1,
293 , 4,
294 GBEN, 1,
295 Offset(0x03),
296 PBEN, 1,
297 , 1,
298 RTEN, 1,
299 , 3,
300 PWDA, 1,
301 }
303 Scope(\_SB) {
304 /* PCIe Configuration Space for 16 busses */
305 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
306 Field(PCFG, ByteAcc, NoLock, Preserve) {
307 /* Byte offsets are computed using the following technique:
308 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
309 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
310 */
311 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
312 STB5, 32,
313 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
314 PT0D, 1,
315 PT1D, 1,
316 PT2D, 1,
317 PT3D, 1,
318 PT4D, 1,
319 PT5D, 1,
320 PT6D, 1,
321 PT7D, 1,
322 PT8D, 1,
323 PT9D, 1,
324 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
325 SBIE, 1,
326 SBME, 1,
327 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
328 SBRI, 8,
329 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
330 SBB1, 32,
331 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
332 ,14,
333 P92E, 1, /* Port92 decode enable */
334 }
336 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
337 Field(SB5, AnyAcc, NoLock, Preserve){
338 /* Port 0 */
339 Offset(0x120), /* Port 0 Task file status */
340 P0ER, 1,
341 , 2,
342 P0DQ, 1,
343 , 3,
344 P0BY, 1,
345 Offset(0x128), /* Port 0 Serial ATA status */
346 P0DD, 4,
347 , 4,
348 P0IS, 4,
349 Offset(0x12C), /* Port 0 Serial ATA control */
350 P0DI, 4,
351 Offset(0x130), /* Port 0 Serial ATA error */
352 , 16,
353 P0PR, 1,
355 /* Port 1 */
356 offset(0x1A0), /* Port 1 Task file status */
357 P1ER, 1,
358 , 2,
359 P1DQ, 1,
360 , 3,
361 P1BY, 1,
362 Offset(0x1A8), /* Port 1 Serial ATA status */
363 P1DD, 4,
364 , 4,
365 P1IS, 4,
366 Offset(0x1AC), /* Port 1 Serial ATA control */
367 P1DI, 4,
368 Offset(0x1B0), /* Port 1 Serial ATA error */
369 , 16,
370 P1PR, 1,
372 /* Port 2 */
373 Offset(0x220), /* Port 2 Task file status */
374 P2ER, 1,
375 , 2,
376 P2DQ, 1,
377 , 3,
378 P2BY, 1,
379 Offset(0x228), /* Port 2 Serial ATA status */
380 P2DD, 4,
381 , 4,
382 P2IS, 4,
383 Offset(0x22C), /* Port 2 Serial ATA control */
384 P2DI, 4,
385 Offset(0x230), /* Port 2 Serial ATA error */
386 , 16,
387 P2PR, 1,
389 /* Port 3 */
390 Offset(0x2A0), /* Port 3 Task file status */
391 P3ER, 1,
392 , 2,
393 P3DQ, 1,
394 , 3,
395 P3BY, 1,
396 Offset(0x2A8), /* Port 3 Serial ATA status */
397 P3DD, 4,
398 , 4,
399 P3IS, 4,
400 Offset(0x2AC), /* Port 3 Serial ATA control */
401 P3DI, 4,
402 Offset(0x2B0), /* Port 3 Serial ATA error */
403 , 16,
404 P3PR, 1,
405 }
406 }
409 #include "acpi/routing.asl"
411 Scope(\_SB) {
413 Method(OSFL, 0){
415 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
417 if(CondRefOf(\_OSI))
418 {
419 Store(1, OSVR) /* Assume some form of XP */
420 if (\_OSI("Windows 2006")) /* Vista */
421 {
422 Store(2, OSVR)
423 }
424 } else {
425 If(WCMP(\_OS,"Linux")) {
426 Store(3, OSVR) /* Linux */
427 } Else {
428 Store(4, OSVR) /* Gotta be WinCE */
429 }
430 }
431 Return(OSVR)
432 }
434 Method(_PIC, 0x01, NotSerialized)
435 {
436 If (Arg0)
437 {
438 \_SB.CIRQ()
439 }
440 Store(Arg0, PMOD)
441 }
442 Method(CIRQ, 0x00, NotSerialized){
443 Store(0, PINA)
444 Store(0, PINB)
445 Store(0, PINC)
446 Store(0, PIND)
447 Store(0, PINE)
448 Store(0, PINF)
449 Store(0, PING)
450 Store(0, PINH)
451 }
453 Name(IRQB, ResourceTemplate(){
454 IRQ(Level,ActiveLow,Shared){15}
455 })
457 Name(IRQP, ResourceTemplate(){
458 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
459 })
461 Name(PITF, ResourceTemplate(){
462 IRQ(Level,ActiveLow,Exclusive){9}
463 })
465 Device(INTA) {
466 Name(_HID, EISAID("PNP0C0F"))
467 Name(_UID, 1)
469 Method(_STA, 0) {
470 if (PINA) {
471 Return(0x0B) /* sata is invisible */
472 } else {
473 Return(0x09) /* sata is disabled */
474 }
475 } /* End Method(_SB.INTA._STA) */
477 Method(_DIS ,0) {
478 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
479 Store(0, PINA)
480 } /* End Method(_SB.INTA._DIS) */
482 Method(_PRS ,0) {
483 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
484 Return(IRQP)
485 } /* Method(_SB.INTA._PRS) */
487 Method(_CRS ,0) {
488 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
489 CreateWordField(IRQB, 0x1, IRQN)
490 ShiftLeft(1, PINA, IRQN)
491 Return(IRQB)
492 } /* Method(_SB.INTA._CRS) */
494 Method(_SRS, 1) {
495 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
496 CreateWordField(ARG0, 1, IRQM)
498 /* Use lowest available IRQ */
499 FindSetRightBit(IRQM, Local0)
500 if (Local0) {
501 Decrement(Local0)
502 }
503 Store(Local0, PINA)
504 } /* End Method(_SB.INTA._SRS) */
505 } /* End Device(INTA) */
507 Device(INTB) {
508 Name(_HID, EISAID("PNP0C0F"))
509 Name(_UID, 2)
511 Method(_STA, 0) {
512 if (PINB) {
513 Return(0x0B) /* sata is invisible */
514 } else {
515 Return(0x09) /* sata is disabled */
516 }
517 } /* End Method(_SB.INTB._STA) */
519 Method(_DIS ,0) {
520 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
521 Store(0, PINB)
522 } /* End Method(_SB.INTB._DIS) */
524 Method(_PRS ,0) {
525 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
526 Return(IRQP)
527 } /* Method(_SB.INTB._PRS) */
529 Method(_CRS ,0) {
530 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
531 CreateWordField(IRQB, 0x1, IRQN)
532 ShiftLeft(1, PINB, IRQN)
533 Return(IRQB)
534 } /* Method(_SB.INTB._CRS) */
536 Method(_SRS, 1) {
537 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
538 CreateWordField(ARG0, 1, IRQM)
540 /* Use lowest available IRQ */
541 FindSetRightBit(IRQM, Local0)
542 if (Local0) {
543 Decrement(Local0)
544 }
545 Store(Local0, PINB)
546 } /* End Method(_SB.INTB._SRS) */
547 } /* End Device(INTB) */
549 Device(INTC) {
550 Name(_HID, EISAID("PNP0C0F"))
551 Name(_UID, 3)
553 Method(_STA, 0) {
554 if (PINC) {
555 Return(0x0B) /* sata is invisible */
556 } else {
557 Return(0x09) /* sata is disabled */
558 }
559 } /* End Method(_SB.INTC._STA) */
561 Method(_DIS ,0) {
562 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
563 Store(0, PINC)
564 } /* End Method(_SB.INTC._DIS) */
566 Method(_PRS ,0) {
567 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
568 Return(IRQP)
569 } /* Method(_SB.INTC._PRS) */
571 Method(_CRS ,0) {
572 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
573 CreateWordField(IRQB, 0x1, IRQN)
574 ShiftLeft(1, PINC, IRQN)
575 Return(IRQB)
576 } /* Method(_SB.INTC._CRS) */
578 Method(_SRS, 1) {
579 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
580 CreateWordField(ARG0, 1, IRQM)
582 /* Use lowest available IRQ */
583 FindSetRightBit(IRQM, Local0)
584 if (Local0) {
585 Decrement(Local0)
586 }
587 Store(Local0, PINC)
588 } /* End Method(_SB.INTC._SRS) */
589 } /* End Device(INTC) */
591 Device(INTD) {
592 Name(_HID, EISAID("PNP0C0F"))
593 Name(_UID, 4)
595 Method(_STA, 0) {
596 if (PIND) {
597 Return(0x0B) /* sata is invisible */
598 } else {
599 Return(0x09) /* sata is disabled */
600 }
601 } /* End Method(_SB.INTD._STA) */
603 Method(_DIS ,0) {
604 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
605 Store(0, PIND)
606 } /* End Method(_SB.INTD._DIS) */
608 Method(_PRS ,0) {
609 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
610 Return(IRQP)
611 } /* Method(_SB.INTD._PRS) */
613 Method(_CRS ,0) {
614 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
615 CreateWordField(IRQB, 0x1, IRQN)
616 ShiftLeft(1, PIND, IRQN)
617 Return(IRQB)
618 } /* Method(_SB.INTD._CRS) */
620 Method(_SRS, 1) {
621 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
622 CreateWordField(ARG0, 1, IRQM)
624 /* Use lowest available IRQ */
625 FindSetRightBit(IRQM, Local0)
626 if (Local0) {
627 Decrement(Local0)
628 }
629 Store(Local0, PIND)
630 } /* End Method(_SB.INTD._SRS) */
631 } /* End Device(INTD) */
633 Device(INTE) {
634 Name(_HID, EISAID("PNP0C0F"))
635 Name(_UID, 5)
637 Method(_STA, 0) {
638 if (PINE) {
639 Return(0x0B) /* sata is invisible */
640 } else {
641 Return(0x09) /* sata is disabled */
642 }
643 } /* End Method(_SB.INTE._STA) */
645 Method(_DIS ,0) {
646 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
647 Store(0, PINE)
648 } /* End Method(_SB.INTE._DIS) */
650 Method(_PRS ,0) {
651 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
652 Return(IRQP)
653 } /* Method(_SB.INTE._PRS) */
655 Method(_CRS ,0) {
656 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
657 CreateWordField(IRQB, 0x1, IRQN)
658 ShiftLeft(1, PINE, IRQN)
659 Return(IRQB)
660 } /* Method(_SB.INTE._CRS) */
662 Method(_SRS, 1) {
663 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
664 CreateWordField(ARG0, 1, IRQM)
666 /* Use lowest available IRQ */
667 FindSetRightBit(IRQM, Local0)
668 if (Local0) {
669 Decrement(Local0)
670 }
671 Store(Local0, PINE)
672 } /* End Method(_SB.INTE._SRS) */
673 } /* End Device(INTE) */
675 Device(INTF) {
676 Name(_HID, EISAID("PNP0C0F"))
677 Name(_UID, 6)
679 Method(_STA, 0) {
680 if (PINF) {
681 Return(0x0B) /* sata is invisible */
682 } else {
683 Return(0x09) /* sata is disabled */
684 }
685 } /* End Method(_SB.INTF._STA) */
687 Method(_DIS ,0) {
688 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
689 Store(0, PINF)
690 } /* End Method(_SB.INTF._DIS) */
692 Method(_PRS ,0) {
693 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
694 Return(PITF)
695 } /* Method(_SB.INTF._PRS) */
697 Method(_CRS ,0) {
698 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
699 CreateWordField(IRQB, 0x1, IRQN)
700 ShiftLeft(1, PINF, IRQN)
701 Return(IRQB)
702 } /* Method(_SB.INTF._CRS) */
704 Method(_SRS, 1) {
705 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
706 CreateWordField(ARG0, 1, IRQM)
708 /* Use lowest available IRQ */
709 FindSetRightBit(IRQM, Local0)
710 if (Local0) {
711 Decrement(Local0)
712 }
713 Store(Local0, PINF)
714 } /* End Method(_SB.INTF._SRS) */
715 } /* End Device(INTF) */
717 Device(INTG) {
718 Name(_HID, EISAID("PNP0C0F"))
719 Name(_UID, 7)
721 Method(_STA, 0) {
722 if (PING) {
723 Return(0x0B) /* sata is invisible */
724 } else {
725 Return(0x09) /* sata is disabled */
726 }
727 } /* End Method(_SB.INTG._STA) */
729 Method(_DIS ,0) {
730 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
731 Store(0, PING)
732 } /* End Method(_SB.INTG._DIS) */
734 Method(_PRS ,0) {
735 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
736 Return(IRQP)
737 } /* Method(_SB.INTG._CRS) */
739 Method(_CRS ,0) {
740 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
741 CreateWordField(IRQB, 0x1, IRQN)
742 ShiftLeft(1, PING, IRQN)
743 Return(IRQB)
744 } /* Method(_SB.INTG._CRS) */
746 Method(_SRS, 1) {
747 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
748 CreateWordField(ARG0, 1, IRQM)
750 /* Use lowest available IRQ */
751 FindSetRightBit(IRQM, Local0)
752 if (Local0) {
753 Decrement(Local0)
754 }
755 Store(Local0, PING)
756 } /* End Method(_SB.INTG._SRS) */
757 } /* End Device(INTG) */
759 Device(INTH) {
760 Name(_HID, EISAID("PNP0C0F"))
761 Name(_UID, 8)
763 Method(_STA, 0) {
764 if (PINH) {
765 Return(0x0B) /* sata is invisible */
766 } else {
767 Return(0x09) /* sata is disabled */
768 }
769 } /* End Method(_SB.INTH._STA) */
771 Method(_DIS ,0) {
772 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
773 Store(0, PINH)
774 } /* End Method(_SB.INTH._DIS) */
776 Method(_PRS ,0) {
777 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
778 Return(IRQP)
779 } /* Method(_SB.INTH._CRS) */
781 Method(_CRS ,0) {
782 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
783 CreateWordField(IRQB, 0x1, IRQN)
784 ShiftLeft(1, PINH, IRQN)
785 Return(IRQB)
786 } /* Method(_SB.INTH._CRS) */
788 Method(_SRS, 1) {
789 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
790 CreateWordField(ARG0, 1, IRQM)
792 /* Use lowest available IRQ */
793 FindSetRightBit(IRQM, Local0)
794 if (Local0) {
795 Decrement(Local0)
796 }
797 Store(Local0, PINH)
798 } /* End Method(_SB.INTH._SRS) */
799 } /* End Device(INTH) */
801 } /* End Scope(_SB) */
803 #include <southbridge/amd/common/acpi/sleepstates.asl>
805 /* Wake status package */
806 Name(WKST,Package(){Zero, Zero})
808 /*
809 * \_PTS - Prepare to Sleep method
810 *
811 * Entry:
812 * Arg0=The value of the sleeping state S1=1, S2=2, etc
813 *
814 * Exit:
815 * -none-
816 *
817 * The _PTS control method is executed at the beginning of the sleep process
818 * for S1-S5. The sleeping value is passed to the _PTS control method. This
819 * control method may be executed a relatively long time before entering the
820 * sleep state and the OS may abort the operation without notification to
821 * the ACPI driver. This method cannot modify the configuration or power
822 * state of any device in the system.
823 */
824 Method(\_PTS, 1) {
825 /* DBGO("\\_PTS\n") */
826 /* DBGO("From S0 to S") */
827 /* DBGO(Arg0) */
828 /* DBGO("\n") */
830 /* Don't allow PCIRST# to reset USB */
831 if (LEqual(Arg0,3)){
832 Store(0,URRE)
833 }
835 /* Clear sleep SMI status flag and enable sleep SMI trap. */
836 /*Store(One, CSSM)
837 Store(One, SSEN)*/
839 /* On older chips, clear PciExpWakeDisEn */
840 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
841 * Store(0,\_SB.PWDE)
842 *}
843 */
845 /* Clear wake status structure. */
846 Store(0, Index(WKST,0))
847 Store(0, Index(WKST,1))
848 \_SB.PCI0.SIOS (Arg0)
849 } /* End Method(\_PTS) */
851 /*
852 * The following method results in a "not a valid reserved NameSeg"
853 * warning so I have commented it out for the duration. It isn't
854 * used, so it could be removed.
855 *
856 *
857 * \_GTS OEM Going To Sleep method
858 *
859 * Entry:
860 * Arg0=The value of the sleeping state S1=1, S2=2
861 *
862 * Exit:
863 * -none-
864 *
865 * Method(\_GTS, 1) {
866 * DBGO("\\_GTS\n")
867 * DBGO("From S0 to S")
868 * DBGO(Arg0)
869 * DBGO("\n")
870 * }
871 */
873 /*
874 * \_BFS OEM Back From Sleep method
875 *
876 * Entry:
877 * Arg0=The value of the sleeping state S1=1, S2=2
878 *
879 * Exit:
880 * -none-
881 */
882 Method(\_BFS, 1) {
883 /* DBGO("\\_BFS\n") */
884 /* DBGO("From S") */
885 /* DBGO(Arg0) */
886 /* DBGO(" to S0\n") */
887 }
889 /*
890 * \_WAK System Wake method
891 *
892 * Entry:
893 * Arg0=The value of the sleeping state S1=1, S2=2
894 *
895 * Exit:
896 * Return package of 2 DWords
897 * Dword 1 - Status
898 * 0x00000000 wake succeeded
899 * 0x00000001 Wake was signaled but failed due to lack of power
900 * 0x00000002 Wake was signaled but failed due to thermal condition
901 * Dword 2 - Power Supply state
902 * if non-zero the effective S-state the power supply entered
903 */
904 Method(\_WAK, 1) {
905 /* DBGO("\\_WAK\n") */
906 /* DBGO("From S") */
907 /* DBGO(Arg0) */
908 /* DBGO(" to S0\n") */
910 /* Re-enable HPET */
911 Store(1,HPDE)
913 /* Restore PCIRST# so it resets USB */
914 if (LEqual(Arg0,3)){
915 Store(1,URRE)
916 }
918 /* Arbitrarily clear PciExpWakeStatus */
919 Store(PWST, Local1)
920 Store(Local1, PWST)
922 /* if (DeRefOf(Index(WKST,0))) {
923 * Store(0, Index(WKST,1))
924 * } else {
925 * Store(Arg0, Index(WKST,1))
926 * }
927 */
928 \_SB.PCI0.SIOW ()
929 Return(WKST)
930 } /* End Method(\_WAK) */
932 Scope(\_GPE) { /* Start Scope GPE */
933 /* General event 0 */
934 /* Method(_L00) {
935 * DBGO("\\_GPE\\_L00\n")
936 * }
937 */
939 /* General event 1 */
940 /* Method(_L01) {
941 * DBGO("\\_GPE\\_L00\n")
942 * }
943 */
945 /* General event 2 */
946 /* Method(_L02) {
947 * DBGO("\\_GPE\\_L00\n")
948 * }
949 */
951 /* General event 3 */
952 Method(_L03) {
953 /* DBGO("\\_GPE\\_L00\n") */
954 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
955 }
957 /* General event 4 */
958 /* Method(_L04) {
959 * DBGO("\\_GPE\\_L00\n")
960 * }
961 */
963 /* General event 5 */
964 /* Method(_L05) {
965 * DBGO("\\_GPE\\_L00\n")
966 * }
967 */
969 /* General event 6 - Used for GPM6, moved to USB.asl */
970 /* Method(_L06) {
971 * DBGO("\\_GPE\\_L00\n")
972 * }
973 */
975 /* General event 7 - Used for GPM7, moved to USB.asl */
976 /* Method(_L07) {
977 * DBGO("\\_GPE\\_L07\n")
978 * }
979 */
981 /* Legacy PM event */
982 Method(_L08) {
983 /* DBGO("\\_GPE\\_L08\n") */
984 }
986 /* Temp warning (TWarn) event */
987 Method(_L09) {
988 /* DBGO("\\_GPE\\_L09\n") */
989 Notify (\_TZ.TZ00, 0x80)
990 }
992 /* Reserved */
993 /* Method(_L0A) {
994 * DBGO("\\_GPE\\_L0A\n")
995 * }
996 */
998 /* USB controller PME# */
999 Method(_L0B) {
1000 /* DBGO("\\_GPE\\_L0B\n") */
1001 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1002 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1003 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1004 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1006 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1007 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1008 }
1010 /* AC97 controller PME# */
1011 /* Method(_L0C) {
1012 * DBGO("\\_GPE\\_L0C\n")
1013 * }
1014 */
1016 /* OtherTherm PME# */
1017 /* Method(_L0D) {
1018 * DBGO("\\_GPE\\_L0D\n")
1019 * }
1020 */
1022 /* GPM9 SCI event - Moved to USB.asl */
1023 /* Method(_L0E) {
1024 * DBGO("\\_GPE\\_L0E\n")
1025 * }
1026 */
1028 /* PCIe HotPlug event */
1029 /* Method(_L0F) {
1030 * DBGO("\\_GPE\\_L0F\n")
1031 * }
1032 */
1034 /* ExtEvent0 SCI event */
1035 Method(_L10) {
1036 /* DBGO("\\_GPE\\_L10\n") */
1037 }
1040 /* ExtEvent1 SCI event */
1041 Method(_L11) {
1042 /* DBGO("\\_GPE\\_L11\n") */
1043 }
1045 /* PCIe PME# event */
1046 /* Method(_L12) {
1047 * DBGO("\\_GPE\\_L12\n")
1048 * }
1049 */
1051 /* GPM0 SCI event - Moved to USB.asl */
1052 /* Method(_L13) {
1053 * DBGO("\\_GPE\\_L13\n")
1054 * }
1055 */
1057 /* GPM1 SCI event - Moved to USB.asl */
1058 /* Method(_L14) {
1059 * DBGO("\\_GPE\\_L14\n")
1060 * }
1061 */
1063 /* GPM2 SCI event - Moved to USB.asl */
1064 /* Method(_L15) {
1065 * DBGO("\\_GPE\\_L15\n")
1066 * }
1067 */
1069 /* GPM3 SCI event - Moved to USB.asl */
1070 /* Method(_L16) {
1071 * DBGO("\\_GPE\\_L16\n")
1072 * }
1073 */
1075 /* GPM8 SCI event - Moved to USB.asl */
1076 /* Method(_L17) {
1077 * DBGO("\\_GPE\\_L17\n")
1078 * }
1079 */
1081 /* GPIO0 or GEvent8 event */
1082 Method(_L18) {
1083 /* DBGO("\\_GPE\\_L18\n") */
1084 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1085 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1086 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1087 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1088 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1089 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1090 }
1092 /* GPM4 SCI event - Moved to USB.asl */
1093 /* Method(_L19) {
1094 * DBGO("\\_GPE\\_L19\n")
1095 * }
1096 */
1098 /* GPM5 SCI event - Moved to USB.asl */
1099 /* Method(_L1A) {
1100 * DBGO("\\_GPE\\_L1A\n")
1101 * }
1102 */
1104 /* Azalia SCI event */
1105 Method(_L1B) {
1106 /* DBGO("\\_GPE\\_L1B\n") */
1107 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1108 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1109 }
1111 /* GPM6 SCI event - Reassigned to _L06 */
1112 /* Method(_L1C) {
1113 * DBGO("\\_GPE\\_L1C\n")
1114 * }
1115 */
1117 /* GPM7 SCI event - Reassigned to _L07 */
1118 /* Method(_L1D) {
1119 * DBGO("\\_GPE\\_L1D\n")
1120 * }
1121 */
1123 /* GPIO2 or GPIO66 SCI event */
1124 /* Method(_L1E) {
1125 * DBGO("\\_GPE\\_L1E\n")
1126 * }
1127 */
1129 /* SATA SCI event - Moved to sata.asl */
1130 /* Method(_L1F) {
1131 * DBGO("\\_GPE\\_L1F\n")
1132 * }
1133 */
1135 } /* End Scope GPE */
1137 #include "acpi/usb.asl"
1139 /* System Bus */
1140 Scope(\_SB) { /* Start \_SB scope */
1141 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1143 /* _SB.PCI0 */
1144 /* Note: Only need HID on Primary Bus */
1145 Device(PCI0) {
1146 External (TOM1)
1147 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1148 Name(_HID, EISAID("PNP0A03"))
1149 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1150 Method(_BBN, 0) { /* Bus number = 0 */
1151 Return(0)
1152 }
1153 Method(_STA, 0) {
1154 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1155 Return(0x0B) /* Status is visible */
1156 }
1158 Method(_PRT,0) {
1159 If(PMOD){ Return(APR0) } /* APIC mode */
1160 Return (PR0) /* PIC Mode */
1161 } /* end _PRT */
1163 /* Describe the Northbridge devices */
1164 Device(AMRT) {
1165 Name(_ADR, 0x00000000)
1166 } /* end AMRT */
1168 /* The internal GFX bridge */
1169 Device(AGPB) {
1170 Name(_ADR, 0x00010000)
1171 Name(_PRW, Package() {0x18, 4})
1172 Method(_PRT,0) {
1173 Return (APR1)
1174 }
1175 } /* end AGPB */
1177 /* The external GFX bridge */
1178 Device(PBR2) {
1179 Name(_ADR, 0x00020000)
1180 Name(_PRW, Package() {0x18, 4})
1181 Method(_PRT,0) {
1182 If(PMOD){ Return(APS2) } /* APIC mode */
1183 Return (PS2) /* PIC Mode */
1184 } /* end _PRT */
1185 } /* end PBR2 */
1187 /* Dev3 is also an external GFX bridge, not used in Herring */
1189 Device(PBR4) {
1190 Name(_ADR, 0x00040000)
1191 Name(_PRW, Package() {0x18, 4})
1192 Method(_PRT,0) {
1193 If(PMOD){ Return(APS4) } /* APIC mode */
1194 Return (PS4) /* PIC Mode */
1195 } /* end _PRT */
1196 } /* end PBR4 */
1198 Device(PBR5) {
1199 Name(_ADR, 0x00050000)
1200 Name(_PRW, Package() {0x18, 4})
1201 Method(_PRT,0) {
1202 If(PMOD){ Return(APS5) } /* APIC mode */
1203 Return (PS5) /* PIC Mode */
1204 } /* end _PRT */
1205 } /* end PBR5 */
1207 Device(PBR6) {
1208 Name(_ADR, 0x00060000)
1209 Name(_PRW, Package() {0x18, 4})
1210 Method(_PRT,0) {
1211 If(PMOD){ Return(APS6) } /* APIC mode */
1212 Return (PS6) /* PIC Mode */
1213 } /* end _PRT */
1214 } /* end PBR6 */
1216 /* The onboard EtherNet chip */
1217 Device(PBR7) {
1218 Name(_ADR, 0x00070000)
1219 Name(_PRW, Package() {0x18, 4})
1220 Method(_PRT,0) {
1221 If(PMOD){ Return(APS7) } /* APIC mode */
1222 Return (PS7) /* PIC Mode */
1223 } /* end _PRT */
1224 } /* end PBR7 */
1226 /* GPP */
1227 Device(PBR9) {
1228 Name(_ADR, 0x00090000)
1229 Name(_PRW, Package() {0x18, 4})
1230 Method(_PRT,0) {
1231 If(PMOD){ Return(APS9) } /* APIC mode */
1232 Return (PS9) /* PIC Mode */
1233 } /* end _PRT */
1234 } /* end PBR9 */
1236 Device(PBRa) {
1237 Name(_ADR, 0x000A0000)
1238 Name(_PRW, Package() {0x18, 4})
1239 Method(_PRT,0) {
1240 If(PMOD){ Return(APSa) } /* APIC mode */
1241 Return (PSa) /* PIC Mode */
1242 } /* end _PRT */
1243 } /* end PBRa */
1246 /* PCI slot 1, 2, 3 */
1247 Device(PIBR) {
1248 Name(_ADR, 0x00140004)
1249 Name(_PRW, Package() {0x18, 4})
1251 Method(_PRT, 0) {
1252 Return (PCIB)
1253 }
1254 }
1256 /* Describe the Southbridge devices */
1257 Device(STCR) {
1258 Name(_ADR, 0x00110000)
1259 #include "acpi/sata.asl"
1260 } /* end STCR */
1262 Device(UOH1) {
1263 Name(_ADR, 0x00130000)
1264 Name(_PRW, Package() {0x0B, 3})
1265 } /* end UOH1 */
1267 Device(UOH2) {
1268 Name(_ADR, 0x00130001)
1269 Name(_PRW, Package() {0x0B, 3})
1270 } /* end UOH2 */
1272 Device(UOH3) {
1273 Name(_ADR, 0x00130002)
1274 Name(_PRW, Package() {0x0B, 3})
1275 } /* end UOH3 */
1277 Device(UOH4) {
1278 Name(_ADR, 0x00130003)
1279 Name(_PRW, Package() {0x0B, 3})
1280 } /* end UOH4 */
1282 Device(UOH5) {
1283 Name(_ADR, 0x00130004)
1284 Name(_PRW, Package() {0x0B, 3})
1285 } /* end UOH5 */
1287 Device(UEH1) {
1288 Name(_ADR, 0x00130005)
1289 Name(_PRW, Package() {0x0B, 3})
1290 } /* end UEH1 */
1292 Device(SBUS) {
1293 Name(_ADR, 0x00140000)
1294 } /* end SBUS */
1296 /* Primary (and only) IDE channel */
1297 Device(IDEC) {
1298 Name(_ADR, 0x00140001)
1299 #include "acpi/ide.asl"
1300 } /* end IDEC */
1302 Device(AZHD) {
1303 Name(_ADR, 0x00140002)
1304 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1305 Field(AZPD, AnyAcc, NoLock, Preserve) {
1306 offset (0x42),
1307 NSDI, 1,
1308 NSDO, 1,
1309 NSEN, 1,
1310 offset (0x44),
1311 IPCR, 4,
1312 offset (0x54),
1313 PWST, 2,
1314 , 6,
1315 PMEB, 1,
1316 , 6,
1317 PMST, 1,
1318 offset (0x62),
1319 MMCR, 1,
1320 offset (0x64),
1321 MMLA, 32,
1322 offset (0x68),
1323 MMHA, 32,
1324 offset (0x6C),
1325 MMDT, 16,
1326 }
1328 Method(_INI) {
1329 If(LEqual(OSVR,3)){ /* If we are running Linux */
1330 Store(zero, NSEN)
1331 Store(one, NSDO)
1332 Store(one, NSDI)
1333 }
1334 }
1335 } /* end AZHD */
1337 Device(LIBR) {
1338 Name(_ADR, 0x00140003)
1339 /* Method(_INI) {
1340 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1341 } */ /* End Method(_SB.SBRDG._INI) */
1343 /* Real Time Clock Device */
1344 Device(RTC0) {
1345 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1346 Name(_CRS, ResourceTemplate() {
1347 IRQNoFlags(){8}
1348 IO(Decode16,0x0070, 0x0070, 0, 2)
1349 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1350 })
1351 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1353 Device(TMR) { /* Timer */
1354 Name(_HID,EISAID("PNP0100")) /* System Timer */
1355 Name(_CRS, ResourceTemplate() {
1356 IRQNoFlags(){0}
1357 IO(Decode16, 0x0040, 0x0040, 0, 4)
1358 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1359 })
1360 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1362 Device(SPKR) { /* Speaker */
1363 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1364 Name(_CRS, ResourceTemplate() {
1365 IO(Decode16, 0x0061, 0x0061, 0, 1)
1366 })
1367 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1369 Device(PIC) {
1370 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1371 Name(_CRS, ResourceTemplate() {
1372 IRQNoFlags(){2}
1373 IO(Decode16,0x0020, 0x0020, 0, 2)
1374 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1375 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1376 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1377 })
1378 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1380 Device(MAD) { /* 8257 DMA */
1381 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1382 Name(_CRS, ResourceTemplate() {
1383 DMA(Compatibility,BusMaster,Transfer8){4}
1384 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1385 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1386 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1387 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1388 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1389 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1390 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1391 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1393 Device(COPR) {
1394 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1395 Name(_CRS, ResourceTemplate() {
1396 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1397 IRQNoFlags(){13}
1398 })
1399 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1401 Device(HPTM) {
1402 Name(_HID,EISAID("PNP0103"))
1403 Name(CRS,ResourceTemplate() {
1404 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1405 })
1406 Method(_STA, 0) {
1407 Return(0x0F) /* sata is visible */
1408 }
1409 Method(_CRS, 0) {
1410 CreateDwordField(CRS, ^HPT._BAS, HPBX)
1411 Store(HPBA, HPBX)
1412 Return(CRS)
1413 }
1414 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1415 } /* end LIBR */
1417 Device(HPBR) {
1418 Name(_ADR, 0x00140004)
1419 } /* end HostPciBr */
1421 Device(ACAD) {
1422 Name(_ADR, 0x00140005)
1423 } /* end Ac97audio */
1425 Device(ACMD) {
1426 Name(_ADR, 0x00140006)
1427 } /* end Ac97modem */
1429 /* ITE8718 Support */
1430 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1431 Field (IOID, ByteAcc, NoLock, Preserve)
1432 {
1433 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1434 }
1436 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1437 {
1438 Offset (0x07),
1439 LDN, 8, /* Logical Device Number */
1440 Offset (0x20),
1441 CID1, 8, /* Chip ID Byte 1, 0x87 */
1442 CID2, 8, /* Chip ID Byte 2, 0x12 */
1443 Offset (0x30),
1444 ACTR, 8, /* Function activate */
1445 Offset (0xF0),
1446 APC0, 8, /* APC/PME Event Enable Register */
1447 APC1, 8, /* APC/PME Status Register */
1448 APC2, 8, /* APC/PME Control Register 1 */
1449 APC3, 8, /* Environment Controller Special Configuration Register */
1450 APC4, 8 /* APC/PME Control Register 2 */
1451 }
1453 /* Enter the 8718 MB PnP Mode */
1454 Method (EPNP)
1455 {
1456 Store(0x87, SIOI)
1457 Store(0x01, SIOI)
1458 Store(0x55, SIOI)
1459 Store(0x55, SIOI) /* 8718 magic number */
1460 }
1461 /* Exit the 8718 MB PnP Mode */
1462 Method (XPNP)
1463 {
1464 Store (0x02, SIOI)
1465 Store (0x02, SIOD)
1466 }
1467 /*
1468 * Keyboard PME is routed to SB700 Gevent3. We can wake
1469 * up the system by pressing the key.
1470 */
1471 Method (SIOS, 1)
1472 {
1473 /* We only enable KBD PME for S5. */
1474 If (LLess (Arg0, 0x05))
1475 {
1476 EPNP()
1477 /* DBGO("8718F\n") */
1479 Store (0x4, LDN)
1480 Store (One, ACTR) /* Enable EC */
1481 /*
1482 Store (0x4, LDN)
1483 Store (0x04, APC4)
1484 */ /* falling edge. which mode? Not sure. */
1486 Store (0x4, LDN)
1487 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1488 Store (0x4, LDN)
1489 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1491 XPNP()
1492 }
1493 }
1494 Method (SIOW, 0)
1495 {
1496 EPNP()
1497 Store (0x4, LDN)
1498 Store (Zero, APC0) /* disable keyboard PME */
1499 Store (0x4, LDN)
1500 Store (0xFF, APC1) /* clear keyboard PME status */
1501 XPNP()
1502 }
1504 Name(CRES, ResourceTemplate() {
1505 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1507 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1508 0x0000, /* address granularity */
1509 0x0000, /* range minimum */
1510 0x0CF7, /* range maximum */
1511 0x0000, /* translation */
1512 0x0CF8 /* length */
1513 )
1515 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1516 0x0000, /* address granularity */
1517 0x0D00, /* range minimum */
1518 0xFFFF, /* range maximum */
1519 0x0000, /* translation */
1520 0xF300 /* length */
1521 )
1523 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1524 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1525 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1526 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1528 /* DRAM Memory from 1MB to TopMem */
1529 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1531 /* BIOS space just below 4GB */
1532 DWORDMemory(
1533 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1534 0x00, /* Granularity */
1535 0x00000000, /* Min */
1536 0x00000000, /* Max */
1537 0x00000000, /* Translation */
1538 0x00000001, /* Max-Min, RLEN */
1539 ,,
1540 PCBM
1541 )
1543 /* DRAM memory from 4GB to TopMem2 */
1544 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1545 0x00000000, /* Granularity */
1546 0x00000000, /* Min */
1547 0x00000000, /* Max */
1548 0x00000000, /* Translation */
1549 0x00000001, /* Max-Min, RLEN */
1550 ,,
1551 DMHI
1552 )
1554 /* BIOS space just below 16EB */
1555 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1556 0x00000000, /* Granularity */
1557 0x00000000, /* Min */
1558 0x00000000, /* Max */
1559 0x00000000, /* Translation */
1560 0x00000001, /* Max-Min, RLEN */
1561 ,,
1562 PEBM
1563 )
1565 }) /* End Name(_SB.PCI0.CRES) */
1567 Method(_CRS, 0) {
1568 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1570 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1571 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1572 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1573 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1574 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1575 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1577 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1578 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1579 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1580 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1582 If(LGreater(LOMH, 0xC0000)){
1583 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1584 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1585 }
1587 /* Set size of memory from 1MB to TopMem */
1588 Subtract(TOM1, 0x100000, DMLL)
1590 /*
1591 * If(LNotEqual(TOM2, 0x00000000)){
1592 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1593 * ShiftLeft(TOM2, 20, Local0)
1594 * Subtract(Local0, 0x100000000, DMHL)
1595 * }
1596 */
1598 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1599 If(LEqual(TOM2, 0x00000000)){
1600 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1601 Store(PBLN,PBML)
1602 }
1603 Else { /* Otherwise, put the BIOS just below 16EB */
1604 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1605 Store(PBLN,EBML)
1606 }
1608 Return(CRES) /* note to change the Name buffer */
1609 } /* end of Method(_SB.PCI0._CRS) */
1611 /*
1612 *
1613 * FIRST METHOD CALLED UPON BOOT
1614 *
1615 * 1. If debugging, print current OS and ACPI interpreter.
1616 * 2. Get PCI Interrupt routing from ACPI VSM, this
1617 * value is based on user choice in BIOS setup.
1618 */
1619 Method(_INI, 0) {
1620 /* DBGO("\\_SB\\_INI\n") */
1621 /* DBGO(" DSDT.ASL code from ") */
1622 /* DBGO(__DATE__) */
1623 /* DBGO(" ") */
1624 /* DBGO(__TIME__) */
1625 /* DBGO("\n Sleep states supported: ") */
1626 /* DBGO("\n") */
1627 /* DBGO(" \\_OS=") */
1628 /* DBGO(\_OS) */
1629 /* DBGO("\n \\_REV=") */
1630 /* DBGO(\_REV) */
1631 /* DBGO("\n") */
1633 /* Determine the OS we're running on */
1634 OSFL()
1636 /* On older chips, clear PciExpWakeDisEn */
1637 /*if (LLessEqual(\SBRI, 0x13)) {
1638 * Store(0,\PWDE)
1639 * }
1640 */
1641 } /* End Method(_SB._INI) */
1642 } /* End Device(PCI0) */
1644 Device(PWRB) { /* Start Power button device */
1645 Name(_HID, EISAID("PNP0C0C"))
1646 Name(_UID, 0xAA)
1647 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1648 Name(_STA, 0x0B) /* sata is invisible */
1649 }
1650 } /* End \_SB scope */
1652 Scope(\_SI) {
1653 Method(_SST, 1) {
1654 /* DBGO("\\_SI\\_SST\n") */
1655 /* DBGO(" New Indicator state: ") */
1656 /* DBGO(Arg0) */
1657 /* DBGO("\n") */
1658 }
1659 } /* End Scope SI */
1661 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1663 /* THERMAL */
1664 Scope(\_TZ) {
1665 Name (KELV, 2732)
1666 Name (THOT, 800)
1667 Name (TCRT, 850)
1669 ThermalZone(TZ00) {
1670 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1671 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1672 Return(Add(0, 2730))
1673 }
1674 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1675 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1676 Return(Package() {\_TZ.TZ00.FAN0})
1677 }
1678 Device (FAN0) {
1679 Name(_HID, EISAID("PNP0C0B"))
1680 Name(_PR0, Package() {PFN0})
1681 }
1683 PowerResource(PFN0,0,0) {
1684 Method(_STA) {
1685 Store(0xF,Local0)
1686 Return(Local0)
1687 }
1688 Method(_ON) {
1689 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1690 }
1691 Method(_OFF) {
1692 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1693 }
1694 }
1696 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1697 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1698 Return (Add (THOT, KELV))
1699 }
1700 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1701 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1702 Return (Add (TCRT, KELV))
1703 }
1704 Method(_TMP,0) { /* return current temp of this zone */
1705 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1706 If (LGreater (Local0, 0x10)) {
1707 Store (Local0, Local1)
1708 }
1709 Else {
1710 Add (Local0, THOT, Local0)
1711 Return (Add (400, KELV))
1712 }
1714 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1715 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1716 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1717 If (LGreater (Local0, 0x10)) {
1718 If (LGreater (Local0, Local1)) {
1719 Store (Local0, Local1)
1720 }
1722 Multiply (Local1, 10, Local1)
1723 Return (Add (Local1, KELV))
1724 }
1725 Else {
1726 Add (Local0, THOT, Local0)
1727 Return (Add (400 , KELV))
1728 }
1729 } /* end of _TMP */
1730 } /* end of TZ00 */
1731 }
1732 }
1733 /* End of ASL file */