src/soc/intel/common/block/cse/cse.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2017-2018 Intel Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <assert.h>
  17 #include <commonlib/helpers.h>
  18 #include <console/console.h>
  19 #include <device/mmio.h>
  20 #include <delay.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <device/pci_ops.h>
  24 #include <intelblocks/cse.h>
  25 #include <soc/iomap.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/me.h>
  28 #include <string.h>
  29 #include <timer.h>
  30
  31 #define MAX_HECI_MESSAGE_RETRY_COUNT 5
  32
  33 /* Wait up to 15 sec for HECI to get ready */
  34 #define HECI_DELAY_READY        (15 * 1000)
  35 /* Wait up to 100 usec between circular buffer polls */
  36 #define HECI_DELAY              100
  37 /* Wait up to 5 sec for CSE to chew something we sent */
  38 #define HECI_SEND_TIMEOUT       (5 * 1000)
  39 /* Wait up to 5 sec for CSE to blurp a reply */
  40 #define HECI_READ_TIMEOUT       (5 * 1000)
  41
  42 #define SLOT_SIZE               sizeof(uint32_t)
  43
  44 #define MMIO_CSE_CB_WW          0x00
  45 #define MMIO_HOST_CSR           0x04
  46 #define MMIO_CSE_CB_RW          0x08
  47 #define MMIO_CSE_CSR            0x0c
  48
  49 #define CSR_IE                  (1 << 0)
  50 #define CSR_IS                  (1 << 1)
  51 #define CSR_IG                  (1 << 2)
  52 #define CSR_READY               (1 << 3)
  53 #define CSR_RESET               (1 << 4)
  54 #define CSR_RP_START            8
  55 #define CSR_RP                  (((1 << 8) - 1) << CSR_RP_START)
  56 #define CSR_WP_START            16
  57 #define CSR_WP                  (((1 << 8) - 1) << CSR_WP_START)
  58 #define CSR_CBD_START           24
  59 #define CSR_CBD                 (((1 << 8) - 1) << CSR_CBD_START)
  60
  61 #define MEI_HDR_IS_COMPLETE     (1 << 31)
  62 #define MEI_HDR_LENGTH_START    16
  63 #define MEI_HDR_LENGTH_SIZE     9
  64 #define MEI_HDR_LENGTH          (((1 << MEI_HDR_LENGTH_SIZE) - 1) \
  65                                         << MEI_HDR_LENGTH_START)
  66 #define MEI_HDR_HOST_ADDR_START 8
  67 #define MEI_HDR_HOST_ADDR       (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START)
  68 #define MEI_HDR_CSE_ADDR_START  0
  69 #define MEI_HDR_CSE_ADDR        (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
  70
  71 static struct cse_device {
  72         uintptr_t sec_bar;
  73 } cse;
  74
  75 /*
  76  * Initialize the device with provided temporary BAR. If BAR is 0 use a
  77  * default. This is intended for pre-mem usage only where BARs haven't been
  78  * assigned yet and devices are not enabled.
  79  */
  80 void heci_init(uintptr_t tempbar)
  81 {
  82 #if defined(__SIMPLE_DEVICE__)
  83         pci_devfn_t dev = PCH_DEV_CSE;
  84 #else
  85         struct device *dev = PCH_DEV_CSE;
  86 #endif
  87         u8 pcireg;
  88
  89         /* Assume it is already initialized, nothing else to do */
  90         if (cse.sec_bar)
  91                 return;
  92
  93         /* Use default pre-ram bar */
  94         if (!tempbar)
  95                 tempbar = HECI1_BASE_ADDRESS;
  96
  97         /* Assign Resources to HECI1 */
  98         /* Clear BIT 1-2 of Command Register */
  99         pcireg = pci_read_config8(dev, PCI_COMMAND);
 100         pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 101         pci_write_config8(dev, PCI_COMMAND, pcireg);
 102
 103         /* Program Temporary BAR for HECI1 */
 104         pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
 105         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
 106
 107         /* Enable Bus Master and MMIO Space */
 108         pcireg = pci_read_config8(dev, PCI_COMMAND);
 109         pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 110         pci_write_config8(dev, PCI_COMMAND, pcireg);
 111
 112         cse.sec_bar = tempbar;
 113 }
 114
 115 /* Get HECI BAR 0 from PCI configuration space */
 116 static uint32_t get_cse_bar(void)
 117 {
 118         uintptr_t bar;
 119
 120         bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0);
 121         assert(bar != 0);
 122         /*
 123          * Bits 31-12 are the base address as per EDS for SPI,
 124          * Don't care about 0-11 bit
 125          */
 126         return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 127 }
 128
 129 static uint32_t read_bar(uint32_t offset)
 130 {
 131         /* Load and cache BAR */
 132         if (!cse.sec_bar)
 133                 cse.sec_bar = get_cse_bar();
 134         return read32((void *)(cse.sec_bar + offset));
 135 }
 136
 137 static void write_bar(uint32_t offset, uint32_t val)
 138 {
 139         /* Load and cache BAR */
 140         if (!cse.sec_bar)
 141                 cse.sec_bar = get_cse_bar();
 142         return write32((void *)(cse.sec_bar + offset), val);
 143 }
 144
 145 static uint32_t read_cse_csr(void)
 146 {
 147         return read_bar(MMIO_CSE_CSR);
 148 }
 149
 150 static uint32_t read_host_csr(void)
 151 {
 152         return read_bar(MMIO_HOST_CSR);
 153 }
 154
 155 static void write_host_csr(uint32_t data)
 156 {
 157         write_bar(MMIO_HOST_CSR, data);
 158 }
 159
 160 static size_t filled_slots(uint32_t data)
 161 {
 162         uint8_t wp, rp;
 163         rp = data >> CSR_RP_START;
 164         wp = data >> CSR_WP_START;
 165         return (uint8_t) (wp - rp);
 166 }
 167
 168 static size_t cse_filled_slots(void)
 169 {
 170         return filled_slots(read_cse_csr());
 171 }
 172
 173 static size_t host_empty_slots(void)
 174 {
 175         uint32_t csr;
 176         csr = read_host_csr();
 177
 178         return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr);
 179 }
 180
 181 static void clear_int(void)
 182 {
 183         uint32_t csr;
 184         csr = read_host_csr();
 185         csr |= CSR_IS;
 186         write_host_csr(csr);
 187 }
 188
 189 static uint32_t read_slot(void)
 190 {
 191         return read_bar(MMIO_CSE_CB_RW);
 192 }
 193
 194 static void write_slot(uint32_t val)
 195 {
 196         write_bar(MMIO_CSE_CB_WW, val);
 197 }
 198
 199 static int wait_write_slots(size_t cnt)
 200 {
 201         struct stopwatch sw;
 202
 203         stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT);
 204         while (host_empty_slots() < cnt) {
 205                 udelay(HECI_DELAY);
 206                 if (stopwatch_expired(&sw)) {
 207                         printk(BIOS_ERR, "HECI: timeout, buffer not drained\n");
 208                         return 0;
 209                 }
 210         }
 211         return 1;
 212 }
 213
 214 static int wait_read_slots(size_t cnt)
 215 {
 216         struct stopwatch sw;
 217
 218         stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT);
 219         while (cse_filled_slots() < cnt) {
 220                 udelay(HECI_DELAY);
 221                 if (stopwatch_expired(&sw)) {
 222                         printk(BIOS_ERR, "HECI: timed out reading answer!\n");
 223                         return 0;
 224                 }
 225         }
 226         return 1;
 227 }
 228
 229 /* get number of full 4-byte slots */
 230 static size_t bytes_to_slots(size_t bytes)
 231 {
 232         return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE;
 233 }
 234
 235 static int cse_ready(void)
 236 {
 237         uint32_t csr;
 238         csr = read_cse_csr();
 239         return csr & CSR_READY;
 240 }
 241
 242 static bool cse_check_hfs1_com(int mode)
 243 {
 244         union me_hfsts1 hfs1;
 245         hfs1.data = me_read_config32(PCI_ME_HFSTS1);
 246         return hfs1.fields.operation_mode == mode;
 247 }
 248
 249 bool cse_is_hfs1_cws_normal(void)
 250 {
 251         union me_hfsts1 hfs1;
 252         hfs1.data = me_read_config32(PCI_ME_HFSTS1);
 253         if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL)
 254                 return true;
 255         return false;
 256 }
 257
 258 bool cse_is_hfs1_com_normal(void)
 259 {
 260         return cse_check_hfs1_com(ME_HFS1_COM_NORMAL);
 261 }
 262
 263 bool cse_is_hfs1_com_secover_mei_msg(void)
 264 {
 265         return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG);
 266 }
 267
 268 bool cse_is_hfs1_com_soft_temp_disable(void)
 269 {
 270         return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE);
 271 }
 272
 273 bool cse_is_hfs3_fw_sku_custom(void)
 274 {
 275         union me_hfsts3 hfs3;
 276         hfs3.data = me_read_config32(PCI_ME_HFSTS3);
 277         return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM;
 278 }
 279
 280 /* Makes the host ready to communicate with CSE */
 281 void cse_set_host_ready(void)
 282 {
 283         uint32_t csr;
 284         csr = read_host_csr();
 285         csr &= ~CSR_RESET;
 286         csr |= (CSR_IG | CSR_READY);
 287         write_host_csr(csr);
 288 }
 289
 290 /* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */
 291 uint8_t cse_wait_sec_override_mode(void)
 292 {
 293         struct stopwatch sw;
 294         stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
 295         while (!cse_is_hfs1_com_secover_mei_msg()) {
 296                 udelay(HECI_DELAY);
 297                 if (stopwatch_expired(&sw)) {
 298                         printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n");
 299                         return 0;
 300                 }
 301         }
 302         printk(BIOS_DEBUG, "HECI: CSE took %lu ms to enter security override mode\n",
 303                         stopwatch_duration_msecs(&sw));
 304         return 1;
 305 }
 306
 307 static int wait_heci_ready(void)
 308 {
 309         struct stopwatch sw;
 310
 311         stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
 312         while (!cse_ready()) {
 313                 udelay(HECI_DELAY);
 314                 if (stopwatch_expired(&sw))
 315                         return 0;
 316         }
 317
 318         return 1;
 319 }
 320
 321 static void host_gen_interrupt(void)
 322 {
 323         uint32_t csr;
 324         csr = read_host_csr();
 325         csr |= CSR_IG;
 326         write_host_csr(csr);
 327 }
 328
 329 static size_t hdr_get_length(uint32_t hdr)
 330 {
 331         return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START;
 332 }
 333
 334 static int
 335 send_one_message(uint32_t hdr, const void *buff)
 336 {
 337         size_t pend_len, pend_slots, remainder, i;
 338         uint32_t tmp;
 339         const uint32_t *p = buff;
 340
 341         /* Get space for the header */
 342         if (!wait_write_slots(1))
 343                 return 0;
 344
 345         /* First, write header */
 346         write_slot(hdr);
 347
 348         pend_len = hdr_get_length(hdr);
 349         pend_slots = bytes_to_slots(pend_len);
 350
 351         if (!wait_write_slots(pend_slots))
 352                 return 0;
 353
 354         /* Write the body in whole slots */
 355         i = 0;
 356         while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) {
 357                 write_slot(*p++);
 358                 i += SLOT_SIZE;
 359         }
 360
 361         remainder = pend_len % SLOT_SIZE;
 362         /* Pad to 4 bytes not touching caller's buffer */
 363         if (remainder) {
 364                 memcpy(&tmp, p, remainder);
 365                 write_slot(tmp);
 366         }
 367
 368         host_gen_interrupt();
 369
 370         /* Make sure nothing bad happened during transmission */
 371         if (!cse_ready())
 372                 return 0;
 373
 374         return pend_len;
 375 }
 376
 377 int
 378 heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr)
 379 {
 380         uint8_t retry;
 381         uint32_t csr, hdr;
 382         size_t sent, remaining, cb_size, max_length;
 383         const uint8_t *p;
 384
 385         if (!msg || !len)
 386                 return 0;
 387
 388         clear_int();
 389
 390         for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) {
 391                 p = msg;
 392
 393                 if (!wait_heci_ready()) {
 394                         printk(BIOS_ERR, "HECI: not ready\n");
 395                         continue;
 396                 }
 397
 398                 csr = read_host_csr();
 399                 cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE;
 400                 /*
 401                  * Reserve one slot for the header. Limit max message
 402                  * length by 9 bits that are available in the header.
 403                  */
 404                 max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1)
 405                                 - SLOT_SIZE;
 406                 remaining = len;
 407
 408                 /*
 409                  * Fragment the message into smaller messages not exceeding
 410                  * useful circular buffer length. Mark last message complete.
 411                  */
 412                 do {
 413                         hdr = MIN(max_length, remaining)
 414                                 << MEI_HDR_LENGTH_START;
 415                         hdr |= client_addr << MEI_HDR_CSE_ADDR_START;
 416                         hdr |= host_addr << MEI_HDR_HOST_ADDR_START;
 417                         hdr |= (MIN(max_length, remaining) == remaining) ?
 418                                                 MEI_HDR_IS_COMPLETE : 0;
 419                         sent = send_one_message(hdr, p);
 420                         p += sent;
 421                         remaining -= sent;
 422                 } while (remaining > 0 && sent != 0);
 423
 424                 if (!remaining)
 425                         return 1;
 426         }
 427         return 0;
 428 }
 429
 430 static size_t
 431 recv_one_message(uint32_t *hdr, void *buff, size_t maxlen)
 432 {
 433         uint32_t reg, *p = buff;
 434         size_t recv_slots, recv_len, remainder, i;
 435
 436         /* first get the header */
 437         if (!wait_read_slots(1))
 438                 return 0;
 439
 440         *hdr = read_slot();
 441         recv_len = hdr_get_length(*hdr);
 442
 443         if (!recv_len)
 444                 printk(BIOS_WARNING, "HECI: message is zero-sized\n");
 445
 446         recv_slots = bytes_to_slots(recv_len);
 447
 448         i = 0;
 449         if (recv_len > maxlen) {
 450                 printk(BIOS_ERR, "HECI: response is too big\n");
 451                 return 0;
 452         }
 453
 454         /* wait for the rest of messages to arrive */
 455         wait_read_slots(recv_slots);
 456
 457         /* fetch whole slots first */
 458         while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) {
 459                 *p++ = read_slot();
 460                 i += SLOT_SIZE;
 461         }
 462
 463         /*
 464          * If ME is not ready, something went wrong and
 465          * we received junk
 466          */
 467         if (!cse_ready())
 468                 return 0;
 469
 470         remainder = recv_len % SLOT_SIZE;
 471
 472         if (remainder) {
 473                 reg = read_slot();
 474                 memcpy(p, &reg, remainder);
 475         }
 476
 477         return recv_len;
 478 }
 479
 480 int heci_receive(void *buff, size_t *maxlen)
 481 {
 482         uint8_t retry;
 483         size_t left, received;
 484         uint32_t hdr = 0;
 485         uint8_t *p;
 486
 487         if (!buff || !maxlen || !*maxlen)
 488                 return 0;
 489
 490         clear_int();
 491
 492         for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) {
 493                 p = buff;
 494                 left = *maxlen;
 495
 496                 if (!wait_heci_ready()) {
 497                         printk(BIOS_ERR, "HECI: not ready\n");
 498                         continue;
 499                 }
 500
 501                 /*
 502                  * Receive multiple packets until we meet one marked
 503                  * complete or we run out of space in caller-provided buffer.
 504                  */
 505                 do {
 506                         received = recv_one_message(&hdr, p, left);
 507                         if (!received) {
 508                                 printk(BIOS_ERR, "HECI: Failed to receive!\n");
 509                                 return 0;
 510                         }
 511                         left -= received;
 512                         p += received;
 513                         /* If we read out everything ping to send more */
 514                         if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots())
 515                                 host_gen_interrupt();
 516                 } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0);
 517
 518                 if ((hdr & MEI_HDR_IS_COMPLETE) && received) {
 519                         *maxlen = p - (uint8_t *) buff;
 520                         return 1;
 521                 }
 522         }
 523         return 0;
 524 }
 525
 526 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz)
 527 {
 528         if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) {
 529                 printk(BIOS_ERR, "HECI: send Failed\n");
 530                 return 0;
 531         }
 532
 533         if (rcv_msg != NULL) {
 534                 if (!heci_receive(rcv_msg, rcv_sz)) {
 535                         printk(BIOS_ERR, "HECI: receive Failed\n");
 536                         return 0;
 537                 }
 538         }
 539         return 1;
 540 }
 541
 542 /*
 543  * Attempt to reset the device. This is useful when host and ME are out
 544  * of sync during transmission or ME didn't understand the message.
 545  */
 546 int heci_reset(void)
 547 {
 548         uint32_t csr;
 549
 550         /* Send reset request */
 551         csr = read_host_csr();
 552         csr |= (CSR_RESET | CSR_IG);
 553         write_host_csr(csr);
 554
 555         if (wait_heci_ready()) {
 556                 /* Device is back on its imaginary feet, clear reset */
 557                 cse_set_host_ready();
 558                 return 1;
 559         }
 560
 561         printk(BIOS_CRIT, "HECI: reset failed\n");
 562
 563         return 0;
 564 }
 565
 566 bool is_cse_enabled(void)
 567 {
 568         const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE);
 569
 570         if (!cse_dev || !cse_dev->enabled) {
 571                 printk(BIOS_WARNING, "HECI: No CSE device\n");
 572                 return false;
 573         }
 574
 575         if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) {
 576                 printk(BIOS_WARNING, "HECI: CSE device is hidden\n");
 577                 return false;
 578         }
 579
 580         return true;
 581 }
 582
 583 uint32_t me_read_config32(int offset)
 584 {
 585         return pci_read_config32(PCH_DEV_CSE, offset);
 586 }
 587
 588 /*
 589  * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/
 590  * HOST_RESET_ONLY/CSE_RESET_ONLY.
 591  */
 592 int cse_request_global_reset(enum rst_req_type rst_type)
 593 {
 594         int status;
 595         struct mkhi_hdr reply;
 596         struct reset_message {
 597                 struct mkhi_hdr hdr;
 598                 uint8_t req_origin;
 599                 uint8_t reset_type;
 600         } __packed;
 601         struct reset_message msg = {
 602                 .hdr = {
 603                         .group_id = MKHI_GROUP_ID_CBM,
 604                         .command = MKHI_CBM_GLOBAL_RESET_REQ,
 605                 },
 606                 .req_origin = GR_ORIGIN_BIOS_POST,
 607                 .reset_type = rst_type
 608         };
 609         size_t reply_size;
 610
 611         printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type);
 612         if (!((rst_type == GLOBAL_RESET) ||
 613                 (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) {
 614                 printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n");
 615                 return 0;
 616         }
 617
 618         heci_reset();
 619
 620         reply_size = sizeof(reply);
 621         memset(&reply, 0, reply_size);
 622
 623         if (rst_type == CSE_RESET_ONLY)
 624                 status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR);
 625         else
 626                 status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size);
 627
 628         printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure");
 629         return status;
 630 }
 631
 632 /* Sends HMRFPO Enable command to CSE */
 633 int cse_hmrfpo_enable(void)
 634 {
 635         struct hmrfpo_enable_msg {
 636                 struct mkhi_hdr hdr;
 637                 uint32_t nonce[2];
 638         } __packed;
 639
 640         /* HMRFPO Enable message */
 641         struct hmrfpo_enable_msg msg = {
 642                 .hdr = {
 643                         .group_id = MKHI_GROUP_ID_HMRFPO,
 644                         .command = MKHI_HMRFPO_ENABLE,
 645                 },
 646                 .nonce = {0},
 647         };
 648
 649         /* HMRFPO Enable response */
 650         struct hmrfpo_enable_resp {
 651                 struct mkhi_hdr hdr;
 652                 /* Base addr for factory data area, not relevant for client SKUs */
 653                 uint32_t fct_base;
 654                 /* Length of factory data area, not relevant for client SKUs */
 655                 uint32_t fct_limit;
 656                 uint8_t status;
 657                 uint8_t padding[3];
 658         } __packed;
 659
 660         struct hmrfpo_enable_resp resp;
 661         size_t resp_size = sizeof(struct hmrfpo_enable_resp);
 662
 663         printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n");
 664         /*
 665          * This command can be run only if:
 666          * - Working state is normal and
 667          * - Operation mode is normal or temporary disable mode.
 668          */
 669         if (!cse_is_hfs1_cws_normal() ||
 670                 (!cse_is_hfs1_com_normal() && !cse_is_hfs1_com_soft_temp_disable())) {
 671                 printk(BIOS_ERR, "HECI: ME not in required Mode\n");
 672                 goto failed;
 673         }
 674
 675         if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg),
 676                                 &resp, &resp_size))
 677                 goto failed;
 678
 679         if (resp.hdr.result) {
 680                 printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result);
 681                 goto failed;
 682         }
 683         return 1;
 684
 685 failed:
 686         return 0;
 687 }
 688
 689 /*
 690  * Sends HMRFPO Get Status command to CSE to get the HMRFPO status.
 691  * The status can be DISABLED/LOCKED/ENABLED
 692  */
 693 int cse_hmrfpo_get_status(void)
 694 {
 695         struct hmrfpo_get_status_msg {
 696                 struct mkhi_hdr hdr;
 697         } __packed;
 698
 699         struct hmrfpo_get_status_resp {
 700                 struct mkhi_hdr hdr;
 701                 uint8_t status;
 702                 uint8_t reserved[3];
 703         } __packed;
 704
 705         struct hmrfpo_get_status_msg msg = {
 706                 .hdr = {
 707                         .group_id = MKHI_GROUP_ID_HMRFPO,
 708                         .command = MKHI_HMRFPO_GET_STATUS,
 709                 },
 710         };
 711         struct hmrfpo_get_status_resp resp;
 712         size_t resp_size = sizeof(struct hmrfpo_get_status_resp);
 713
 714         printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n");
 715
 716         if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg),
 717                                 &resp, &resp_size)) {
 718                 printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n");
 719                 return -1;
 720         }
 721
 722         if (resp.hdr.result) {
 723                 printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n",
 724                                 resp.hdr.result);
 725                 return -1;
 726         }
 727
 728         return resp.status;
 729 }
 730
 731 #if ENV_RAMSTAGE
 732
 733 static void update_sec_bar(struct device *dev)
 734 {
 735         cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
 736 }
 737
 738 static void cse_set_resources(struct device *dev)
 739 {
 740         if (dev->path.pci.devfn == PCH_DEVFN_CSE)
 741                 update_sec_bar(dev);
 742
 743         pci_dev_set_resources(dev);
 744 }
 745
 746 static struct device_operations cse_ops = {
 747         .set_resources          = cse_set_resources,
 748         .read_resources         = pci_dev_read_resources,
 749         .enable_resources       = pci_dev_enable_resources,
 750         .init                   = pci_dev_init,
 751         .ops_pci                = &pci_dev_ops_pci,
 752 };
 753
 754 static const unsigned short pci_device_ids[] = {
 755         PCI_DEVICE_ID_INTEL_APL_CSE0,
 756         PCI_DEVICE_ID_INTEL_GLK_CSE0,
 757         PCI_DEVICE_ID_INTEL_CNL_CSE0,
 758         PCI_DEVICE_ID_INTEL_SKL_CSE0,
 759         PCI_DEVICE_ID_INTEL_LWB_CSE0,
 760         PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER,
 761         PCI_DEVICE_ID_INTEL_CNP_H_CSE0,
 762         PCI_DEVICE_ID_INTEL_ICL_CSE0,
 763         PCI_DEVICE_ID_INTEL_CMP_CSE0,
 764         PCI_DEVICE_ID_INTEL_CMP_H_CSE0,
 765         PCI_DEVICE_ID_INTEL_TGL_CSE0,
 766         PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0,
 767         PCI_DEVICE_ID_INTEL_MCC_CSE0,
 768         PCI_DEVICE_ID_INTEL_MCC_CSE1,
 769         PCI_DEVICE_ID_INTEL_MCC_CSE2,
 770         PCI_DEVICE_ID_INTEL_MCC_CSE3,
 771         0,
 772 };
 773
 774 static const struct pci_driver cse_driver __pci_driver = {
 775         .ops                    = &cse_ops,
 776         .vendor                 = PCI_VENDOR_ID_INTEL,
 777         /* SoC/chipset needs to provide PCI device ID */
 778         .devices                = pci_device_ids
 779 };
 780
 781 #endif