src/soc/intel/alderlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 /*
   9  * This file is created based on Intel Alder Lake Processor PCH Datasheet
  10  * Document number: 621483
  11  * Chapter number: 4
  12  */
  13
  14 #define __SIMPLE_DEVICE__
  15
  16 #include <acpi/acpi_pm.h>
  17 #include <device/mmio.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <device/pci_def.h>
  21 #include <console/console.h>
  22 #include <intelblocks/pmclib.h>
  23 #include <intelblocks/rtc.h>
  24 #include <intelblocks/tco.h>
  25 #include <security/vboot/vbnv.h>
  26 #include <soc/espi.h>
  27 #include <soc/gpe.h>
  28 #include <soc/gpio.h>
  29 #include <soc/iomap.h>
  30 #include <soc/pci_devs.h>
  31 #include <soc/pm.h>
  32 #include <soc/smbus.h>
  33 #include <soc/soc_chip.h>
  34 #include <types.h>
  35
  36 /*
  37  * SMI
  38  */
  39
  40 const char *const *soc_smi_sts_array(size_t *a)
  41 {
  42         static const char *const smi_sts_bits[] = {
  43                 [BIOS_STS_BIT] = "BIOS",
  44                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  45                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  46                 [APM_STS_BIT] = "APM",
  47                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  48                 [PM1_STS_BIT] = "PM1",
  49                 [GPE0_STS_BIT] = "GPE0",
  50                 [GPIO_STS_BIT] = "GPI",
  51                 [MCSMI_STS_BIT] = "MCSMI",
  52                 [DEVMON_STS_BIT] = "DEVMON",
  53                 [TCO_STS_BIT] = "TCO",
  54                 [PERIODIC_STS_BIT] = "PERIODIC",
  55                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  56                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  57                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  58                 [MONITOR_STS_BIT] = "MONITOR",
  59                 [SPI_SMI_STS_BIT] = "SPI",
  60                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  61                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  62         };
  63
  64         *a = ARRAY_SIZE(smi_sts_bits);
  65         return smi_sts_bits;
  66 }
  67
  68 /*
  69  * TCO
  70  */
  71
  72 const char *const *soc_tco_sts_array(size_t *a)
  73 {
  74         static const char *const tco_sts_bits[] = {
  75                 [0] = "NMI2SMI",
  76                 [1] = "SW_TCO",
  77                 [2] = "TCO_INT",
  78                 [3] = "TIMEOUT",
  79                 [7] = "NEWCENTURY",
  80                 [8] = "BIOSWR",
  81                 [9] = "DMISCI",
  82                 [10] = "DMISMI",
  83                 [12] = "DMISERR",
  84                 [13] = "SLVSEL",
  85                 [16] = "INTRD_DET",
  86                 [17] = "SECOND_TO",
  87                 [18] = "BOOT",
  88                 [20] = "SMLINK_SLV"
  89         };
  90
  91         *a = ARRAY_SIZE(tco_sts_bits);
  92         return tco_sts_bits;
  93 }
  94
  95 /*
  96  * GPE0
  97  */
  98
  99 const char *const *soc_std_gpe_sts_array(size_t *a)
 100 {
 101         static const char *const gpe_sts_bits[] = {
 102                 [1] = "HOTPLUG",
 103                 [2] = "SWGPE",
 104                 [6] = "TCO_SCI",
 105                 [7] = "SMB_WAK",
 106                 [9] = "PCI_EXP",
 107                 [10] = "BATLOW",
 108                 [11] = "PME",
 109                 [12] = "ME",
 110                 [13] = "PME_B0",
 111                 [14] = "eSPI",
 112                 [15] = "GPIO Tier-2",
 113                 [16] = "LAN_WAKE",
 114                 [18] = "WADT"
 115         };
 116
 117         *a = ARRAY_SIZE(gpe_sts_bits);
 118         return gpe_sts_bits;
 119 }
 120
 121 void pmc_set_disb(void)
 122 {
 123         /* Set the DISB after DRAM init */
 124         uint8_t disb_val;
 125         /* Only care about bits [23:16] of register GEN_PMCON_A */
 126         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 127
 128         disb_val = read8(addr);
 129         disb_val |= (DISB >> 16);
 130
 131         /* Don't clear bits that are write-1-to-clear */
 132         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 133         write8(addr, disb_val);
 134 }
 135
 136 void pmc_clear_pmcon_sts(void)
 137 {
 138         uint32_t reg_val;
 139         uint8_t *addr;
 140         addr = pmc_mmio_regs();
 141
 142         reg_val = read32(addr + GEN_PMCON_A);
 143         /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
 144          * while retaining MS4V write-1-to-clear bit */
 145         reg_val &= ~(MS4V);
 146
 147         write32((addr + GEN_PMCON_A), reg_val);
 148 }
 149
 150 /*
 151  * PMC controller gets hidden from PCI bus
 152  * during FSP-Silicon init call. Hence PWRMBASE
 153  * can't be accessible using PCI configuration space
 154  * read/write.
 155  */
 156 uint8_t *pmc_mmio_regs(void)
 157 {
 158         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 159 }
 160
 161 uintptr_t soc_read_pmc_base(void)
 162 {
 163         return (uintptr_t)pmc_mmio_regs();
 164 }
 165
 166 uint32_t *soc_pmc_etr_addr(void)
 167 {
 168         return (uint32_t *)(soc_read_pmc_base() + ETR);
 169 }
 170
 171 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 172 {
 173         DEVTREE_CONST struct soc_intel_alderlake_config *config;
 174
 175         config = config_of_soc();
 176
 177         /* Assign to out variable */
 178         *dw0 = config->pmc_gpe0_dw0;
 179         *dw1 = config->pmc_gpe0_dw1;
 180         *dw2 = config->pmc_gpe0_dw2;
 181 }
 182
 183 static int rtc_failed(uint32_t gen_pmcon_b)
 184 {
 185         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 186 }
 187
 188 int soc_get_rtc_failed(void)
 189 {
 190         const struct chipset_power_state *ps;
 191
 192         if (acpi_pm_state_for_rtc(&ps) < 0)
 193                 return 1;
 194
 195         return rtc_failed(ps->gen_pmcon_b);
 196 }
 197
 198 int vbnv_cmos_failed(void)
 199 {
 200         return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 201 }
 202
 203 static inline int deep_s3_enabled(void)
 204 {
 205         uint32_t deep_s3_pol;
 206
 207         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 208         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 209 }
 210
 211 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 212 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 213 {
 214         /*
 215          * Check for any power failure to determine if this a wake from
 216          * S5 because the PCH does not set the WAK_STS bit when waking
 217          * from a true G3 state.
 218          */
 219         if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
 220                 prev_sleep_state = ACPI_S5;
 221
 222         /*
 223          * If waking from S3 determine if deep S3 is enabled. If not,
 224          * need to check both deep sleep well and normal suspend well.
 225          * Otherwise just check deep sleep well.
 226          */
 227         if (prev_sleep_state == ACPI_S3) {
 228                 /* PWR_FLR represents deep sleep power well loss. */
 229                 uint32_t mask = PWR_FLR;
 230
 231                 /* If deep s3 isn't enabled check the suspend well too. */
 232                 if (!deep_s3_enabled())
 233                         mask |= SUS_PWR_FLR;
 234
 235                 if (ps->gen_pmcon_a & mask)
 236                         prev_sleep_state = ACPI_S5;
 237         }
 238
 239         return prev_sleep_state;
 240 }
 241
 242 void soc_fill_power_state(struct chipset_power_state *ps)
 243 {
 244         uint8_t *pmc;
 245
 246         ps->tco1_sts = tco_read_reg(TCO1_STS);
 247         ps->tco2_sts = tco_read_reg(TCO2_STS);
 248
 249         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 250
 251         pmc = pmc_mmio_regs();
 252         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 253         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 254         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 255         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 256         ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 257
 258         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 259                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 260
 261         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 262                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 263
 264         printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 265 }
 266
 267 /* STM Support */
 268 uint16_t get_pmbase(void)
 269 {
 270         return (uint16_t) ACPI_BASE_ADDRESS;
 271 }
 272
 273 /*
 274  * Set which power state system will be after reapplying
 275  * the power (from G3 State)
 276  */
 277 void pmc_soc_set_afterg3_en(const bool on)
 278 {
 279         uint8_t reg8;
 280         uint8_t *const pmcbase = pmc_mmio_regs();
 281
 282         reg8 = read8(pmcbase + GEN_PMCON_A);
 283         if (on)
 284                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 285         else
 286                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 287         write8(pmcbase + GEN_PMCON_A, reg8);
 288 }