src/mainboard/intel/strago/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2015 Intel Corp.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/acpi.h>
  18 #include <arch/io.h>
  19 #include <console/console.h>
  20 #include <cpu/x86/smm.h>
  21 #include "ec.h"
  22
  23 #include <ec/google/chromeec/ec.h>
  24 #include <elog.h>
  25
  26 #include <soc/nvs.h>
  27 #include <soc/pm.h>
  28 #include <soc/gpio.h>
  29
  30 #include "onboard.h"
  31
  32 /* The wake gpio is SUS_GPIO[0]. */
  33 #define WAKE_GPIO_EN SUS_GPIO_EN0
  34
  35 int mainboard_io_trap_handler(int smif)
  36 {
  37         switch (smif) {
  38         case 0x99:
  39                 printk(BIOS_DEBUG, "Sample\n");
  40                 smm_get_gnvs()->smif = 0;
  41                 break;
  42         default:
  43                 return 0;
  44         }
  45
  46         /*
  47          * On success, the IO Trap Handler returns 0
  48          * On failure, the IO Trap Handler returns a value != 0
  49          *
  50          * For now, we force the return value to 0 and log all traps to
  51          * see what's going on.
  52          */
  53         //gnvs->smif = 0;
  54         return 1;
  55 }
  56
  57 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
  58 static uint8_t mainboard_smi_ec(void)
  59 {
  60         uint8_t cmd = google_chromeec_get_event();
  61         uint16_t pmbase = get_pmbase();
  62         uint32_t pm1_cnt;
  63
  64 #if IS_ENABLED(CONFIG_ELOG_GSMI)
  65         /* Log this event */
  66         if (cmd)
  67                 elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
  68 #endif
  69
  70         switch (cmd) {
  71         case EC_HOST_EVENT_LID_CLOSED:
  72                 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
  73
  74                 /* Go to S5 */
  75                 pm1_cnt = inl(pmbase + PM1_CNT);
  76                 pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
  77                 outl(pm1_cnt, pmbase + PM1_CNT);
  78                 break;
  79         }
  80
  81         return cmd;
  82 }
  83 #endif
  84
  85 /*
  86  * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
  87  * this includes the enable bits in the lower 16 bits.
  88  */
  89 void mainboard_smi_gpi(uint32_t alt_gpio_smi)
  90 {
  91 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
  92         if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
  93                 /* Process all pending events */
  94                 while (mainboard_smi_ec() != 0)
  95                         ;
  96         }
  97 #endif
  98 }
  99
 100 void mainboard_smi_sleep(uint8_t slp_typ)
 101 {
 102         /* Disable USB charging if required */
 103         switch (slp_typ) {
 104         case ACPI_S3:
 105 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 106                 if (smm_get_gnvs()->s3u0 == 0)
 107                         google_chromeec_set_usb_charge_mode(
 108                                 0, USB_CHARGE_MODE_DISABLED);
 109                 if (smm_get_gnvs()->s3u1 == 0)
 110                         google_chromeec_set_usb_charge_mode(
 111                                 1, USB_CHARGE_MODE_DISABLED);
 112
 113                 /* Enable wake events */
 114                 google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 115 #endif
 116                 /* Enable wake pin in GPE block. */
 117                 enable_gpe(WAKE_GPIO_EN);
 118                 break;
 119         case ACPI_S5:
 120 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 121                 if (smm_get_gnvs()->s5u0 == 0)
 122                         google_chromeec_set_usb_charge_mode(
 123                                 0, USB_CHARGE_MODE_DISABLED);
 124                 if (smm_get_gnvs()->s5u1 == 0)
 125                         google_chromeec_set_usb_charge_mode(
 126                                 1, USB_CHARGE_MODE_DISABLED);
 127
 128                 /* Enable wake events */
 129                 google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
 130 #endif
 131                 break;
 132         }
 133
 134 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 135         /* Disable SCI and SMI events */
 136         google_chromeec_set_smi_mask(0);
 137         google_chromeec_set_sci_mask(0);
 138
 139         /* Clear pending events that may trigger immediate wake */
 140         while (google_chromeec_get_event() != 0)
 141                 ;
 142
 143         /* Set LPC lines to low power in S3/S5. */
 144         if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
 145                 lpc_set_low_power();
 146 #endif
 147 }
 148
 149 int mainboard_smi_apmc(uint8_t apmc)
 150 {
 151         switch (apmc) {
 152         case APM_CNT_ACPI_ENABLE:
 153 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 154                 google_chromeec_set_smi_mask(0);
 155                 /* Clear all pending events */
 156                 while (google_chromeec_get_event() != 0)
 157                         ;
 158                 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 159 #endif
 160                 break;
 161         case APM_CNT_ACPI_DISABLE:
 162 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 163                 google_chromeec_set_sci_mask(0);
 164                 /* Clear all pending events */
 165                 while (google_chromeec_get_event() != 0)
 166                         ;
 167                 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 168 #endif
 169                 break;
 170         }
 171         return 0;
 172 }