mainboards: align on using ACPI_Sx definitions
[coreboot.git] / src / mainboard / google / rikku / pei_data.c
blob4eeabbeec4971bcf97e3c0d603feaa0b22f930dd
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2015 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <stdint.h>
17 #include <string.h>
18 #include <soc/gpio.h>
19 #include <soc/pei_data.h>
20 #include <soc/pei_wrapper.h>
22 void mainboard_fill_pei_data(struct pei_data *pei_data)
24 pei_data->ec_present = 0;
26 /* P0: VP8 */
27 pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
28 USB_PORT_MINI_PCIE);
29 /* P1: Port A, CN22 */
30 pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
31 USB_PORT_INTERNAL);
32 /* P2: Port B, CN23 */
33 pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
34 USB_PORT_INTERNAL);
35 /* P3: WLAN */
36 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
37 USB_PORT_MINI_PCIE);
38 /* P4: Port C, CN25 */
39 pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
40 USB_PORT_INTERNAL);
41 /* P5: Port D, CN25 */
42 pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
43 USB_PORT_INTERNAL);
44 /* P6: Card Reader */
45 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
46 USB_PORT_INTERNAL);
47 /* P7: EMPTY */
48 pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
49 USB_PORT_SKIP);
51 /* P1: CN22 */
52 pei_data_usb3_port(pei_data, 0, 1, 0, 0);
53 /* P2: CN23 */
54 pei_data_usb3_port(pei_data, 1, 1, 1, 0);
55 /* P3: CN25 */
56 pei_data_usb3_port(pei_data, 2, 1, 2, 0);
57 /* P4: CN25 */
58 pei_data_usb3_port(pei_data, 3, 1, 2, 0);