src/mainboard/google/rikku/chromeos.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <string.h>
  17 #include <arch/io.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <console/console.h>
  21 #include <vendorcode/google/chromeos/chromeos.h>
  22 #include <ec/google/chromeec/ec.h>
  23 #include <soc/gpio.h>
  24 #include <soc/sata.h>
  25
  26 #define GPIO_SPI_WP     58
  27 #define GPIO_REC_MODE   12
  28
  29 #define FLAG_SPI_WP     0
  30 #define FLAG_REC_MODE   1
  31 #define FLAG_DEV_MODE   2
  32
  33 #ifndef __PRE_RAM__
  34 #include <boot/coreboot_tables.h>
  35
  36 void fill_lb_gpios(struct lb_gpios *gpios)
  37 {
  38         struct lb_gpio chromeos_gpios[] = {
  39                 {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"},
  40                 {GPIO_REC_MODE, ACTIVE_LOW,
  41                         get_recovery_mode_switch(), "recovery"},
  42                 {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
  43                 {-1, ACTIVE_HIGH, 1, "lid"},
  44                 {-1, ACTIVE_HIGH, 0, "power"},
  45                 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
  46         };
  47         lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
  48 }
  49 #endif
  50
  51 int get_write_protect_state(void)
  52 {
  53         device_t dev;
  54 #ifdef __PRE_RAM__
  55         dev = PCI_DEV(0, 0x1f, 2);
  56 #else
  57         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
  58 #endif
  59         return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
  60 }
  61
  62 int get_developer_mode_switch(void)
  63 {
  64         return 0;
  65 }
  66
  67 int get_recovery_mode_switch(void)
  68 {
  69         device_t dev;
  70 #ifdef __PRE_RAM__
  71         dev = PCI_DEV(0, 0x1f, 2);
  72 #else
  73         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
  74 #endif
  75         return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
  76 }
  77
  78 #ifdef __PRE_RAM__
  79 void save_chromeos_gpios(void)
  80 {
  81         u32 flags = 0;
  82
  83         /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
  84         if (get_gpio(GPIO_SPI_WP))
  85                 flags |= (1 << FLAG_SPI_WP);
  86
  87         /* Recovery: GPIO12 = RECOVERY_L, active low */
  88         if (!get_gpio(GPIO_REC_MODE))
  89                 flags |= (1 << FLAG_REC_MODE);
  90
  91         /* Developer: Virtual */
  92
  93         pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
  94 }
  95 #endif