src/soc/intel/common/block/include/intelblocks/cse.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SOC_INTEL_COMMON_CSE_H
   4 #define SOC_INTEL_COMMON_CSE_H
   5
   6 #include <types.h>
   7
   8 /* MKHI Command groups */
   9 #define MKHI_GROUP_ID_CBM       0x0
  10 #define MKHI_GROUP_ID_HMRFPO    0x5
  11 #define MKHI_GROUP_ID_GEN       0xff
  12 #define MKHI_GROUP_ID_BUP_COMMON        0xf0
  13
  14 /* Global Reset Command ID */
  15 #define MKHI_CBM_GLOBAL_RESET_REQ       0xb
  16
  17 /* Origin of Global Reset command */
  18 #define GR_ORIGIN_BIOS_POST     0x2
  19
  20 /* HMRFPO Command Ids */
  21 #define MKHI_HMRFPO_ENABLE      0x1
  22 #define MKHI_HMRFPO_GET_STATUS  0x3
  23
  24 /* Get Firmware Version Command Id */
  25 #define MKHI_GEN_GET_FW_VERSION 0x2
  26
  27 /* Boot partition info and set boot partition info command ids */
  28 #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c
  29 #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d
  30 #define MKHI_BUP_COMMON_DATA_CLEAR              0x20
  31
  32 /* ME Current Working States */
  33 #define ME_HFS1_CWS_NORMAL      0x5
  34
  35 /* ME Current Operation Modes */
  36 #define ME_HFS1_COM_NORMAL      0x0
  37 #define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
  38 #define ME_HFS1_COM_SECOVER_MEI_MSG     0x5
  39
  40 /* ME Firmware SKU Types */
  41 #define ME_HFS3_FW_SKU_CONSUMER 0x2
  42 #define ME_HFS3_FW_SKU_CORPORATE        0x3
  43 #define ME_HFS3_FW_SKU_LITE     0x5
  44
  45 /* HFSTS register offsets in PCI config space */
  46 enum {
  47         PCI_ME_HFSTS1 = 0x40,
  48         PCI_ME_HFSTS2 = 0x48,
  49         PCI_ME_HFSTS3 = 0x60,
  50         PCI_ME_HFSTS4 = 0x64,
  51         PCI_ME_HFSTS5 = 0x68,
  52         PCI_ME_HFSTS6 = 0x6C,
  53 };
  54
  55 /* MKHI Message Header */
  56 struct mkhi_hdr {
  57         uint8_t group_id;
  58         uint8_t command:7;
  59         uint8_t is_resp:1;
  60         uint8_t rsvd;
  61         uint8_t result;
  62 } __packed;
  63
  64 /* set up device for use in early boot enviroument with temp bar */
  65 void heci_init(uintptr_t bar);
  66 /*
  67  * Receive message into buff not exceeding maxlen. Message is considered
  68  * successfully received if a 'complete' indication is read from ME side
  69  * and there was enough space in the buffer to fit that message. maxlen
  70  * is updated with size of message that was received. Returns 0 on failure
  71  * and 1 on success.
  72  * In case of error heci_reset() may be requiered.
  73  */
  74 int heci_receive(void *buff, size_t *maxlen);
  75 /*
  76  * Send message msg of size len to host from host_addr to cse_addr.
  77  * Returns 1 on success and 0 otherwise.
  78  * In case of error heci_reset() may be requiered.
  79  */
  80 int
  81 heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
  82
  83 /*
  84  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
  85  * rcv_msg of size rcv_sz
  86  * Returns 0 on failure and 1 on success.
  87  */
  88 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
  89
  90 /*
  91  * Attempt device reset. This is useful and perhaps only thing left to do when
  92  * CPU and CSE are out of sync or CSE fails to respond.
  93  * Returns 0 on failure and 1 on success.
  94  */
  95 int heci_reset(void);
  96 /* Disable HECI using Sideband interface communication */
  97 void heci_disable(void);
  98
  99 /* Reads config value from a specified offset in the CSE PCI Config space. */
 100 uint32_t me_read_config32(int offset);
 101
 102 /*
 103  * Check if the CSE device is enabled in device tree. Also check if the device
 104  * is visible on the PCI bus by reading config space.
 105  * Return true if device present and config space enabled, else return false.
 106  */
 107 bool is_cse_enabled(void);
 108
 109 /* Makes the host ready to communicate with CSE */
 110 void cse_set_host_ready(void);
 111
 112 /*
 113  * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
 114  * Returns 0 on failure and 1 on success.
 115  */
 116 uint8_t cse_wait_sec_override_mode(void);
 117
 118 enum rst_req_type {
 119         GLOBAL_RESET = 1,
 120         CSE_RESET_ONLY = 3,
 121 };
 122
 123 /*
 124  * Sends GLOBAL_RESET_REQ cmd to CSE.
 125  * The reset type can be one of the above defined reset type.
 126  * Returns 0 on failure and 1 on success.
 127  */
 128 int cse_request_global_reset(enum rst_req_type rst_type);
 129
 130 /*
 131  * Sends HMRFPO_ENABLE command.
 132  * HMRFPO - Host ME Region Flash Protection Override.
 133  * For CSE Lite SKU, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode:
 134  *      1. Ensure CSE boots from RO(BP1).
 135  *              - Set CSE's next boot partition to RO
 136  *              - Issue GLOBAL_RESET command to reset the system
 137  *      2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.
 138  *
 139  * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks
 140  * the CSE region to perform updates to it.
 141  * This command is only valid before EOP.
 142  *
 143  * Returns 0 on failure to send HECI command and to enable HMRFPO mode, and 1 on success.
 144  *
 145  */
 146 int cse_hmrfpo_enable(void);
 147
 148 /*
 149  * Send HMRFPO_GET_STATUS command.
 150  * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED)
 151  * on success.
 152  */
 153 int cse_hmrfpo_get_status(void);
 154
 155 /* Fixed Address MEI Header's Host Address field value */
 156 #define BIOS_HOST_ADDR  0x00
 157
 158 /* Fixed Address MEI Header's ME Address field value */
 159 #define HECI_MKHI_ADDR  0x07
 160
 161 /* HMRFPO Status types */
 162 /* Host can't access ME region */
 163 #define MKHI_HMRFPO_DISABLED    0
 164
 165 /*
 166  * ME Firmware locked down HMRFPO Feature.
 167  * Host can't access ME region.
 168  */
 169 #define MKHI_HMRFPO_LOCKED      1
 170
 171 /* Host can access ME region */
 172 #define MKHI_HMRFPO_ENABLED     2
 173
 174 /*
 175  * Queries and logs ME firmware version
 176  */
 177 void print_me_fw_version(void *unused);
 178
 179 /*
 180  * Checks current working operation state is normal or not.
 181  * Returns true if CSE's current working state is normal, otherwise false.
 182  */
 183 bool cse_is_hfs1_cws_normal(void);
 184
 185 /*
 186  * Checks CSE's current operation mode is normal or not.
 187  * Returns true if CSE's current operation mode is normal, otherwise false.
 188  */
 189 bool cse_is_hfs1_com_normal(void);
 190
 191 /*
 192  * Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
 193  * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
 194  */
 195 bool cse_is_hfs1_com_secover_mei_msg(void);
 196
 197 /*
 198  * Checks CSE's current operation mode is Soft Disable Mode or not.
 199  * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
 200  */
 201 bool cse_is_hfs1_com_soft_temp_disable(void);
 202
 203 /*
 204  * Checks CSE's Firmware SKU is Lite or not.
 205  * Returns true if CSE's Firmware SKU is Lite, otherwise false
 206  */
 207 bool cse_is_hfs3_fw_sku_lite(void);
 208
 209 /*
 210  * Polls for CSE's current operation mode 'Soft Temp Disable'.
 211  * Returns 0 on failure and 1 on success.
 212  */
 213 uint8_t cse_wait_com_soft_temp_disable(void);
 214
 215 /*
 216  * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
 217  * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
 218  * boot from RW and triggers recovery mode if CSE fails to jump to RW.
 219  * In software triggered recovery mode, the function allows CSE to boot from whatever is
 220  * currently selected partition.
 221  */
 222 void cse_fw_sync(void *unused);
 223
 224 /* Perform a board-specific reset sequence for CSE RO<->RW jump */
 225 void cse_board_reset(void);
 226
 227 #endif // SOC_INTEL_COMMON_CSE_H