2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
33 #include <cpu/x86/lapic.h>
34 #include <cpu/amd/mtrr.h>
40 #include <cpu/amd/amdfam15.h>
41 #include <cpuRegisters.h>
42 #include "agesawrapper.h"
43 #include "northbridge.h"
45 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
47 #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
48 #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
51 typedef struct dram_base_mask
{
52 u32 base
; //[47:27] at [28:8]
53 u32 mask
; //[47:27] at [28:8] and enable at bit 0
56 static unsigned node_nums
;
57 static unsigned sblink
;
58 static device_t __f0_dev
[MAX_NODE_NUMS
];
59 static device_t __f1_dev
[MAX_NODE_NUMS
];
60 static device_t __f2_dev
[MAX_NODE_NUMS
];
61 static device_t __f4_dev
[MAX_NODE_NUMS
];
62 static unsigned fx_devs
= 0;
64 static dram_base_mask_t
get_dram_base_mask(u32 nodeid
)
70 temp
= pci_read_config32(dev
, 0x44 + (nodeid
<< 3)); //[39:24] at [31:16]
71 d
.mask
= ((temp
& 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
72 temp
= pci_read_config32(dev
, 0x144 + (nodeid
<<3)) & 0xff; //[47:40] at [7:0]
74 temp
= pci_read_config32(dev
, 0x40 + (nodeid
<< 3)); //[39:24] at [31:16]
75 d
.mask
|= (temp
& 1); // enable bit
76 d
.base
= ((temp
& 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
77 temp
= pci_read_config32(dev
, 0x140 + (nodeid
<<3)) & 0xff; //[47:40] at [7:0]
82 static void set_io_addr_reg(device_t dev
, u32 nodeid
, u32 linkn
, u32 reg
,
83 u32 io_min
, u32 io_max
)
87 /* io range allocation */
88 tempreg
= (nodeid
&0xf) | ((nodeid
& 0x30)<<(8-4)) | (linkn
<<4) | ((io_max
&0xf0)<<(12-4)); //limit
89 for (i
=0; i
<node_nums
; i
++)
90 pci_write_config32(__f1_dev
[i
], reg
+4, tempreg
);
91 tempreg
= 3 /*| ( 3<<4)*/ | ((io_min
&0xf0)<<(12-4)); //base :ISA and VGA ?
93 // FIXME: can we use VGA reg instead?
94 if (dev
->link
[link
].bridge_ctrl
& PCI_BRIDGE_CTL_VGA
) {
95 printk(BIOS_SPEW
, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
96 __func__
, dev_path(dev
), link
);
97 tempreg
|= PCI_IO_BASE_VGA_EN
;
99 if (dev
->link
[link
].bridge_ctrl
& PCI_BRIDGE_CTL_NO_ISA
) {
100 tempreg
|= PCI_IO_BASE_NO_ISA
;
103 for (i
=0; i
<node_nums
; i
++)
104 pci_write_config32(__f1_dev
[i
], reg
, tempreg
);
107 static void set_mmio_addr_reg(u32 nodeid
, u32 linkn
, u32 reg
, u32 index
, u32 mmio_min
, u32 mmio_max
, u32 nodes
)
111 /* io range allocation */
112 tempreg
= (nodeid
&0xf) | (linkn
<<4) | (mmio_max
&0xffffff00); //limit
113 for (i
=0; i
<nodes
; i
++)
114 pci_write_config32(__f1_dev
[i
], reg
+4, tempreg
);
115 tempreg
= 3 | (nodeid
& 0x30) | (mmio_min
&0xffffff00);
116 for (i
=0; i
<node_nums
; i
++)
117 pci_write_config32(__f1_dev
[i
], reg
, tempreg
);
120 static device_t
get_node_pci(u32 nodeid
, u32 fn
)
122 #if MAX_NODE_NUMS + CONFIG_CDB >= 32
123 if ((CONFIG_CDB
+ nodeid
) < 32) {
124 return dev_find_slot(CONFIG_CBB
, PCI_DEVFN(CONFIG_CDB
+ nodeid
, fn
));
126 return dev_find_slot(CONFIG_CBB
-1, PCI_DEVFN(CONFIG_CDB
+ nodeid
- 32, fn
));
129 return dev_find_slot(CONFIG_CBB
, PCI_DEVFN(CONFIG_CDB
+ nodeid
, fn
));
133 static void get_fx_devs(void)
136 for (i
= 0; i
< MAX_NODE_NUMS
; i
++) {
137 __f0_dev
[i
] = get_node_pci(i
, 0);
138 __f1_dev
[i
] = get_node_pci(i
, 1);
139 __f2_dev
[i
] = get_node_pci(i
, 2);
140 __f4_dev
[i
] = get_node_pci(i
, 4);
141 if (__f0_dev
[i
] != NULL
&& __f1_dev
[i
] != NULL
)
144 if (__f1_dev
[0] == NULL
|| __f0_dev
[0] == NULL
|| fx_devs
== 0) {
145 die("Cannot find 0:0x18.[0|1]\n");
147 printk(BIOS_DEBUG
, "fx_devs=0x%x\n", fx_devs
);
150 static u32
f1_read_config32(unsigned reg
)
154 return pci_read_config32(__f1_dev
[0], reg
);
157 static void f1_write_config32(unsigned reg
, u32 value
)
162 for(i
= 0; i
< fx_devs
; i
++) {
165 if (dev
&& dev
->enabled
) {
166 pci_write_config32(dev
, reg
, value
);
171 static u32
amdfam15_nodeid(device_t dev
)
173 #if MAX_NODE_NUMS == 64
175 busn
= dev
->bus
->secondary
;
176 if (busn
!= CONFIG_CBB
) {
177 return (dev
->path
.pci
.devfn
>> 3) - CONFIG_CDB
+ 32;
179 return (dev
->path
.pci
.devfn
>> 3) - CONFIG_CDB
;
183 return (dev
->path
.pci
.devfn
>> 3) - CONFIG_CDB
;
187 static void set_vga_enable_reg(u32 nodeid
, u32 linkn
)
191 val
= 1 | (nodeid
<<4) | (linkn
<<12);
193 * (1)mmio 0xa0000:0xbffff
194 * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
196 f1_write_config32(0xf4, val
);
202 * @retval 2 resoure not exist, usable
203 * @retval 0 resource exist, not usable
204 * @retval 1 resource exist, resource has been allocated before
206 static int reg_useable(unsigned reg
, device_t goal_dev
, unsigned goal_nodeid
,
209 struct resource
*res
;
210 unsigned nodeid
, link
= 0;
213 for (nodeid
= 0; !res
&& (nodeid
< fx_devs
); nodeid
++) {
215 dev
= __f0_dev
[nodeid
];
218 for (link
= 0; !res
&& (link
< 8); link
++) {
219 res
= probe_resource(dev
, IOINDEX(0x1000 + reg
, link
));
225 if ((goal_link
== (link
- 1)) &&
226 (goal_nodeid
== (nodeid
- 1)) &&
234 static struct resource
*amdfam15_find_iopair(device_t dev
, unsigned nodeid
, unsigned link
)
236 struct resource
*resource
;
240 for (reg
= 0xc0; reg
<= 0xd8; reg
+= 0x8) {
242 result
= reg_useable(reg
, dev
, nodeid
, link
);
244 /* I have been allocated this one */
247 else if (result
> 1) {
248 /* I have a free register pair */
253 reg
= free_reg
; // if no free, the free_reg still be 0
256 resource
= new_resource(dev
, IOINDEX(0x1000 + reg
, link
));
261 static struct resource
*amdfam15_find_mempair(device_t dev
, u32 nodeid
, u32 link
)
263 struct resource
*resource
;
267 for (reg
= 0x80; reg
<= 0xb8; reg
+= 0x8) {
269 result
= reg_useable(reg
, dev
, nodeid
, link
);
271 /* I have been allocated this one */
274 else if (result
> 1) {
275 /* I have a free register pair */
283 resource
= new_resource(dev
, IOINDEX(0x1000 + reg
, link
));
287 static void amdfam15_link_read_bases(device_t dev
, u32 nodeid
, u32 link
)
289 struct resource
*resource
;
291 /* Initialize the io space constraints on the current bus */
292 resource
= amdfam15_find_iopair(dev
, nodeid
, link
);
295 align
= log2(HT_IO_HOST_ALIGN
);
298 resource
->align
= align
;
299 resource
->gran
= align
;
300 resource
->limit
= 0xffffUL
;
301 resource
->flags
= IORESOURCE_IO
| IORESOURCE_BRIDGE
;
304 /* Initialize the prefetchable memory constraints on the current bus */
305 resource
= amdfam15_find_mempair(dev
, nodeid
, link
);
309 resource
->align
= log2(HT_MEM_HOST_ALIGN
);
310 resource
->gran
= log2(HT_MEM_HOST_ALIGN
);
311 resource
->limit
= 0xffffffffffULL
;
312 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
313 resource
->flags
|= IORESOURCE_BRIDGE
;
316 /* Initialize the memory constraints on the current bus */
317 resource
= amdfam15_find_mempair(dev
, nodeid
, link
);
321 resource
->align
= log2(HT_MEM_HOST_ALIGN
);
322 resource
->gran
= log2(HT_MEM_HOST_ALIGN
);
323 resource
->limit
= 0xffffffffffULL
;
324 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_BRIDGE
;
329 static void read_resources(device_t dev
)
334 nodeid
= amdfam15_nodeid(dev
);
335 for (link
= dev
->link_list
; link
; link
= link
->next
) {
336 if (link
->children
) {
337 amdfam15_link_read_bases(dev
, nodeid
, link
->link_num
);
342 static void set_resource(device_t dev
, struct resource
*resource
, u32 nodeid
)
344 resource_t rbase
, rend
;
345 unsigned reg
, link_num
;
348 /* Make certain the resource has actually been set */
349 if (!(resource
->flags
& IORESOURCE_ASSIGNED
)) {
353 /* If I have already stored this resource don't worry about it */
354 if (resource
->flags
& IORESOURCE_STORED
) {
358 /* Only handle PCI memory and IO resources */
359 if (!(resource
->flags
& (IORESOURCE_MEM
| IORESOURCE_IO
)))
362 /* Ensure I am actually looking at a resource of function 1 */
363 if ((resource
->index
& 0xffff) < 0x1000) {
366 /* Get the base address */
367 rbase
= resource
->base
;
369 /* Get the limit (rounded up) */
370 rend
= resource_end(resource
);
372 /* Get the register and link */
373 reg
= resource
->index
& 0xfff; // 4k
374 link_num
= IOINDEX_LINK(resource
->index
);
376 if (resource
->flags
& IORESOURCE_IO
) {
377 set_io_addr_reg(dev
, nodeid
, link_num
, reg
, rbase
>>8, rend
>>8);
379 else if (resource
->flags
& IORESOURCE_MEM
) {
380 set_mmio_addr_reg(nodeid
, link_num
, reg
, (resource
->index
>>24), rbase
>>8, rend
>>8, node_nums
) ;// [39:8]
382 resource
->flags
|= IORESOURCE_STORED
;
383 sprintf(buf
, " <node %x link %x>",
385 report_resource_stored(dev
, resource
, buf
);
389 * I tried to reuse the resource allocation code in set_resource()
390 * but it is too difficult to deal with the resource allocation magic.
393 static void create_vga_resource(device_t dev
, unsigned nodeid
)
397 /* find out which link the VGA card is connected,
398 * we only deal with the 'first' vga card */
399 for (link
= dev
->link_list
; link
; link
= link
->next
) {
400 if (link
->bridge_ctrl
& PCI_BRIDGE_CTL_VGA
) {
401 #if CONFIG_MULTIPLE_VGA_ADAPTERS
402 extern device_t vga_pri
; // the primary vga device, defined in device.c
403 printk(BIOS_DEBUG
, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri
->bus
->secondary
,
404 link
->secondary
,link
->subordinate
);
405 /* We need to make sure the vga_pri is under the link */
406 if((vga_pri
->bus
->secondary
>= link
->secondary
) &&
407 (vga_pri
->bus
->secondary
<= link
->subordinate
)
414 /* no VGA card installed */
418 printk(BIOS_DEBUG
, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev
), nodeid
, sblink
);
419 set_vga_enable_reg(nodeid
, sblink
);
422 static void set_resources(device_t dev
)
426 struct resource
*res
;
428 /* Find the nodeid */
429 nodeid
= amdfam15_nodeid(dev
);
431 create_vga_resource(dev
, nodeid
); //TODO: do we need this?
433 /* Set each resource we have found */
434 for (res
= dev
->resource_list
; res
; res
= res
->next
) {
435 set_resource(dev
, res
, nodeid
);
438 for (bus
= dev
->link_list
; bus
; bus
= bus
->next
) {
440 assign_resources(bus
);
445 static void northbridge_init(struct device
*dev
)
450 static struct device_operations northbridge_operations
= {
451 .read_resources
= read_resources
,
452 .set_resources
= set_resources
,
453 .enable_resources
= pci_dev_enable_resources
,
454 .init
= northbridge_init
,
459 static const struct pci_driver family15_northbridge __pci_driver
= {
460 .ops
= &northbridge_operations
,
461 .vendor
= PCI_VENDOR_ID_AMD
,
462 .device
= PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT
,
465 static const struct pci_driver family10_northbridge __pci_driver
= {
466 .ops
= &northbridge_operations
,
467 .vendor
= PCI_VENDOR_ID_AMD
,
468 .device
= PCI_DEVICE_ID_AMD_10H_NB_HT
,
471 struct chip_operations northbridge_amd_agesa_family15tn_ops
= {
472 CHIP_NAME("AMD FAM15 Northbridge")
476 static void domain_read_resources(device_t dev
)
480 /* Find the already assigned resource pairs */
482 for (reg
= 0x80; reg
<= 0xd8; reg
+= 0x08) {
484 base
= f1_read_config32(reg
);
485 limit
= f1_read_config32(reg
+ 0x04);
486 /* Is this register allocated? */
487 if ((base
& 3) != 0) {
488 unsigned nodeid
, reg_link
;
490 if (reg
<0xc0) { // mmio
491 nodeid
= (limit
& 0xf) + (base
&0x30);
493 nodeid
= (limit
& 0xf) + ((base
>>4)&0x30);
495 reg_link
= (limit
>> 4) & 7;
496 reg_dev
= __f0_dev
[nodeid
];
498 /* Reserve the resource */
499 struct resource
*res
;
500 res
= new_resource(reg_dev
, IOINDEX(0x1000 + reg
, reg_link
));
507 /* FIXME: do we need to check extend conf space?
508 I don't believe that much preset value */
510 #if !CONFIG_PCI_64BIT_PREF_MEM
511 pci_domain_read_resources(dev
);
515 struct resource
*resource
;
516 for (link
=dev
->link_list
; link
; link
= link
->next
) {
517 /* Initialize the system wide io space constraints */
518 resource
= new_resource(dev
, 0|(link
->link_num
<<2));
519 resource
->base
= 0x400;
520 resource
->limit
= 0xffffUL
;
521 resource
->flags
= IORESOURCE_IO
;
523 /* Initialize the system wide prefetchable memory resources constraints */
524 resource
= new_resource(dev
, 1|(link
->link_num
<<2));
525 resource
->limit
= 0xfcffffffffULL
;
526 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
528 /* Initialize the system wide memory resources constraints */
529 resource
= new_resource(dev
, 2|(link
->link_num
<<2));
530 resource
->limit
= 0xfcffffffffULL
;
531 resource
->flags
= IORESOURCE_MEM
;
536 extern u8 acpi_slp_type
;
538 static void domain_enable_resources(device_t dev
)
541 #if CONFIG_HAVE_ACPI_RESUME
542 if (acpi_slp_type
== 3)
543 agesawrapper_fchs3laterestore();
546 /* Must be called after PCI enumeration and resource allocation */
547 printk(BIOS_DEBUG
, "\nFam15 - domain_enable_resources: AmdInitMid.\n");
548 #if CONFIG_HAVE_ACPI_RESUME
549 if (acpi_slp_type
!= 3) {
550 printk(BIOS_DEBUG
, "agesawrapper_amdinitmid ");
551 val
= agesawrapper_amdinitmid ();
553 printk(BIOS_DEBUG
, "error level: %x \n", val
);
555 printk(BIOS_DEBUG
, "passed.\n");
558 printk(BIOS_DEBUG
, "agesawrapper_amdinitmid ");
559 val
= agesawrapper_amdinitmid ();
561 printk(BIOS_DEBUG
, "error level: %x \n", val
);
563 printk(BIOS_DEBUG
, "passed.\n");
566 printk(BIOS_DEBUG
, " ader - leaving domain_enable_resources.\n");
569 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
570 struct hw_mem_hole_info
{
571 unsigned hole_startk
;
574 static struct hw_mem_hole_info
get_hw_mem_hole_info(void)
576 struct hw_mem_hole_info mem_hole
;
578 mem_hole
.hole_startk
= CONFIG_HW_MEM_HOLE_SIZEK
;
579 mem_hole
.node_id
= -1;
580 for (i
= 0; i
< node_nums
; i
++) {
583 d
= get_dram_base_mask(i
);
584 if (!(d
.mask
& 1)) continue; // no memory on this node
585 hole
= pci_read_config32(__f1_dev
[i
], 0xf0);
586 if (hole
& 1) { // we find the hole
587 mem_hole
.hole_startk
= (hole
& (0xff<<24)) >> 10;
588 mem_hole
.node_id
= i
; // record the node No with hole
589 break; // only one hole
592 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
593 if (mem_hole
.node_id
== -1) {
594 resource_t limitk_pri
= 0;
595 for (i
=0; i
<node_nums
; i
++) {
597 resource_t base_k
, limit_k
;
598 d
= get_dram_base_mask(i
);
599 if (!(d
.base
& 1)) continue;
600 base_k
= ((resource_t
)(d
.base
& 0x1fffff00)) <<9;
601 if (base_k
> 4 *1024 * 1024) break; // don't need to go to check
602 if (limitk_pri
!= base_k
) { // we find the hole
603 mem_hole
.hole_startk
= (unsigned)limitk_pri
; // must beblow 4G
604 mem_hole
.node_id
= i
;
605 break; //only one hole
607 limit_k
= ((resource_t
)(((d
.mask
& ~1) + 0x000FF) & 0x1fffff00)) << 9;
608 limitk_pri
= limit_k
;
615 #define ONE_MB_SHIFT 20
617 static void setup_uma_memory(void)
620 uint32_t topmem
= (uint32_t) bsp_topmem();
623 /* refer to UMA Size Consideration in Family15h BKDG. */
624 /* Please reference MemNGetUmaSizeOR () */
626 * Total system memory UMASize
631 sys_mem
= topmem
+ (16 << ONE_MB_SHIFT
); // Ignore 16MB allocated for C6 when finding UMA size
632 if ((bsp_topmem2()>>32) || (sys_mem
>= 2048 << ONE_MB_SHIFT
)) {
633 uma_memory_size
= 512 << ONE_MB_SHIFT
;
634 } else if (sys_mem
>= 1024 << ONE_MB_SHIFT
) {
635 uma_memory_size
= 256 << ONE_MB_SHIFT
;
637 uma_memory_size
= 64 << ONE_MB_SHIFT
;
639 uma_memory_base
= topmem
- uma_memory_size
; /* TOP_MEM1 */
641 printk(BIOS_INFO
, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
642 __func__
, uma_memory_size
, uma_memory_base
);
647 static void domain_set_resources(device_t dev
)
649 #if CONFIG_PCI_64BIT_PREF_MEM
650 struct resource
*io
, *mem1
, *mem2
;
651 struct resource
*res
;
653 unsigned long mmio_basek
;
657 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
658 struct hw_mem_hole_info mem_hole
;
659 u32 reset_memhole
= 1;
662 #if CONFIG_PCI_64BIT_PREF_MEM
664 for (link
= dev
->link_list
; link
; link
= link
->next
) {
665 /* Now reallocate the pci resources memory with the
666 * highest addresses I can manage.
668 mem1
= find_resource(dev
, 1|(link
->link_num
<<2));
669 mem2
= find_resource(dev
, 2|(link
->link_num
<<2));
671 printk(BIOS_DEBUG
, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
672 mem1
->base
, mem1
->limit
, mem1
->size
, mem1
->align
);
673 printk(BIOS_DEBUG
, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
674 mem2
->base
, mem2
->limit
, mem2
->size
, mem2
->align
);
676 /* See if both resources have roughly the same limits */
677 if (((mem1
->limit
<= 0xffffffff) && (mem2
->limit
<= 0xffffffff)) ||
678 ((mem1
->limit
> 0xffffffff) && (mem2
->limit
> 0xffffffff)))
680 /* If so place the one with the most stringent alignment first */
681 if (mem2
->align
> mem1
->align
) {
682 struct resource
*tmp
;
687 /* Now place the memory as high up as it will go */
688 mem2
->base
= resource_max(mem2
);
689 mem1
->limit
= mem2
->base
- 1;
690 mem1
->base
= resource_max(mem1
);
693 /* Place the resources as high up as they will go */
694 mem2
->base
= resource_max(mem2
);
695 mem1
->base
= resource_max(mem1
);
698 printk(BIOS_DEBUG
, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
699 mem1
->base
, mem1
->limit
, mem1
->size
, mem1
->align
);
700 printk(BIOS_DEBUG
, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
701 mem2
->base
, mem2
->limit
, mem2
->size
, mem2
->align
);
704 for (res
= &dev
->resource_list
; res
; res
= res
->next
)
706 res
->flags
|= IORESOURCE_ASSIGNED
;
707 res
->flags
|= IORESOURCE_STORED
;
708 report_resource_stored(dev
, res
, "");
712 pci_tolm
= 0xffffffffUL
;
713 for (link
= dev
->link_list
; link
; link
= link
->next
) {
714 pci_tolm
= find_pci_tolm(link
);
717 // FIXME handle interleaved nodes. If you fix this here, please fix
719 mmio_basek
= pci_tolm
>> 10;
720 /* Round mmio_basek to something the processor can support */
721 mmio_basek
&= ~((1 << 6) -1);
723 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
724 // MMIO hole. If you fix this here, please fix amdk8, too.
725 /* Round the mmio hole to 64M */
726 mmio_basek
&= ~((64*1024) - 1);
728 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
729 /* if the hw mem hole is already set in raminit stage, here we will compare
730 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
731 * use hole_basek as mmio_basek and we don't need to reset hole.
732 * otherwise We reset the hole to the mmio_basek
735 mem_hole
= get_hw_mem_hole_info();
737 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
738 if ((mem_hole
.node_id
!= -1) && (mmio_basek
> mem_hole
.hole_startk
)) {
739 mmio_basek
= mem_hole
.hole_startk
;
745 for (i
= 0; i
< node_nums
; i
++) {
747 resource_t basek
, limitk
, sizek
; // 4 1T
749 d
= get_dram_base_mask(i
);
751 if (!(d
.mask
& 1)) continue;
752 basek
= ((resource_t
)(d
.base
& 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
753 limitk
= ((resource_t
)(((d
.mask
& ~1) + 0x000FF) & 0x1fffff00)) << 9 ;
755 sizek
= limitk
- basek
;
757 /* see if we need a hole from 0xa0000 to 0xbffff */
758 if ((basek
< ((8*64)+(8*16))) && (sizek
> ((8*64)+(16*16)))) {
759 ram_resource(dev
, (idx
| i
), basek
, ((8*64)+(8*16)) - basek
);
761 basek
= (8*64)+(16*16);
762 sizek
= limitk
- ((8*64)+(16*16));
766 //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
768 /* split the region to accomodate pci memory space */
769 if ((basek
< 4*1024*1024 ) && (limitk
> mmio_basek
)) {
770 if (basek
<= mmio_basek
) {
772 pre_sizek
= mmio_basek
- basek
;
774 ram_resource(dev
, (idx
| i
), basek
, pre_sizek
);
777 #if CONFIG_WRITE_HIGH_TABLES
778 if (high_tables_base
==0) {
779 /* Leave some space for ACPI, PIRQ and MP tables */
781 high_tables_base
= uma_memory_base
- HIGH_MEMORY_SIZE
;
783 high_tables_base
= (mmio_basek
* 1024) - HIGH_MEMORY_SIZE
;
785 high_tables_size
= HIGH_MEMORY_SIZE
;
786 printk(BIOS_DEBUG
, " split: %dK table at =%08llx\n",
787 (u32
)(high_tables_size
/ 1024), high_tables_base
);
793 if ((basek
+ sizek
) <= 4*1024*1024) {
798 sizek
-= (4*1024*1024 - mmio_basek
);
802 ram_resource(dev
, (idx
| i
), basek
, sizek
);
804 #if CONFIG_WRITE_HIGH_TABLES
805 printk(BIOS_DEBUG
, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
806 i
, mmio_basek
, basek
, limitk
);
807 if (high_tables_base
==0) {
808 /* Leave some space for ACPI, PIRQ and MP tables */
810 high_tables_base
= uma_memory_base
- HIGH_MEMORY_SIZE
;
812 high_tables_base
= (limitk
* 1024) - HIGH_MEMORY_SIZE
;
814 high_tables_size
= HIGH_MEMORY_SIZE
;
820 uma_resource(dev
, 7, uma_memory_base
>> 10, uma_memory_size
>> 10);
823 for(link
= dev
->link_list
; link
; link
= link
->next
) {
824 if (link
->children
) {
825 assign_resources(link
);
830 static struct device_operations pci_domain_ops
= {
831 .read_resources
= domain_read_resources
,
832 .set_resources
= domain_set_resources
,
833 .enable_resources
= domain_enable_resources
,
835 .scan_bus
= pci_domain_scan_bus
,
837 #if CONFIG_MMCONF_SUPPORT_DEFAULT
838 .ops_pci_bus
= &pci_ops_mmconf
,
840 .ops_pci_bus
= &pci_cf8_conf1
,
844 static void sysconf_init(device_t dev
) // first node
846 sblink
= (pci_read_config32(dev
, 0x64)>>8) & 7; // don't forget sublink1
847 node_nums
= ((pci_read_config32(dev
, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
850 static void add_more_links(device_t dev
, unsigned total_links
)
852 struct bus
*link
, *last
= NULL
;
855 for (link
= dev
->link_list
; link
; link
= link
->next
)
859 int links
= total_links
- last
->link_num
;
860 link_num
= last
->link_num
;
862 link
= malloc(links
*sizeof(*link
));
864 die("Couldn't allocate more links!\n");
865 memset(link
, 0, links
*sizeof(*link
));
871 link
= malloc(total_links
*sizeof(*link
));
872 memset(link
, 0, total_links
*sizeof(*link
));
873 dev
->link_list
= link
;
876 for (link_num
= link_num
+ 1; link_num
< total_links
; link_num
++) {
877 link
->link_num
= link_num
;
879 link
->next
= link
+ 1;
886 static u32
cpu_bus_scan(device_t dev
, u32 max
)
896 unsigned ApicIdCoreIdSize
;
902 dev_mc
= dev_find_slot(0, PCI_DEVFN(CONFIG_CDB
, 0)); //0x00
903 if (dev_mc
&& dev_mc
->bus
) {
904 printk(BIOS_DEBUG
, "%s found", dev_path(dev_mc
));
905 pci_domain
= dev_mc
->bus
->dev
;
906 if (pci_domain
&& (pci_domain
->path
.type
== DEVICE_PATH_PCI_DOMAIN
)) {
907 printk(BIOS_DEBUG
, "\n%s move to ",dev_path(dev_mc
));
908 dev_mc
->bus
->secondary
= CONFIG_CBB
; // move to 0xff
909 printk(BIOS_DEBUG
, "%s",dev_path(dev_mc
));
911 printk(BIOS_DEBUG
, " but it is not under pci_domain directly ");
913 printk(BIOS_DEBUG
, "\n");
915 dev_mc
= dev_find_slot(CONFIG_CBB
, PCI_DEVFN(CONFIG_CDB
, 0));
917 dev_mc
= dev_find_slot(0, PCI_DEVFN(0x18, 0));
918 if (dev_mc
&& dev_mc
->bus
) {
919 printk(BIOS_DEBUG
, "%s found\n", dev_path(dev_mc
));
920 pci_domain
= dev_mc
->bus
->dev
;
921 if (pci_domain
&& (pci_domain
->path
.type
== DEVICE_PATH_PCI_DOMAIN
)) {
922 if ((pci_domain
->link_list
) && (pci_domain
->link_list
->children
== dev_mc
)) {
923 printk(BIOS_DEBUG
, "%s move to ",dev_path(dev_mc
));
924 dev_mc
->bus
->secondary
= CONFIG_CBB
; // move to 0xff
925 printk(BIOS_DEBUG
, "%s\n",dev_path(dev_mc
));
927 printk(BIOS_DEBUG
, "%s move to ",dev_path(dev_mc
));
928 dev_mc
->path
.pci
.devfn
-= PCI_DEVFN(0x18,0);
929 printk(BIOS_DEBUG
, "%s\n",dev_path(dev_mc
));
930 dev_mc
= dev_mc
->sibling
;
937 dev_mc
= dev_find_slot(CONFIG_CBB
, PCI_DEVFN(CONFIG_CDB
, 0));
939 printk(BIOS_ERR
, "%02x:%02x.0 not found", CONFIG_CBB
, CONFIG_CDB
);
942 sysconf_init(dev_mc
);
943 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
944 if (node_nums
>32) { // need to put node 32 to node 63 to bus 0xfe
945 if (pci_domain
->link_list
&& !pci_domain
->link_list
->next
) {
946 struct bus
*new_link
= new_link(pci_domain
);
947 pci_domain
->link_list
->next
= new_link
;
948 new_link
->link_num
= 1;
949 new_link
->dev
= pci_domain
;
950 new_link
->children
= 0;
951 printk(BIOS_DEBUG
, "%s links now 2\n", dev_path(pci_domain
));
953 pci_domain
->link_list
->next
->secondary
= CONFIG_CBB
- 1;
957 /* Get Max Number of cores(MNC) */
958 coreid_bits
= (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT
) & 0x0000F000) >> 12;
959 core_max
= 1 << (coreid_bits
& 0x000F); //mnc
961 ApicIdCoreIdSize
= ((cpuid_ecx(0x80000008)>>12) & 0xF);
962 if (ApicIdCoreIdSize
) {
963 core_nums
= (1 << ApicIdCoreIdSize
) - 1;
965 core_nums
= 3; //quad core
968 /* Find which cpus are present */
969 cpu_bus
= dev
->link_list
;
970 for (i
= 0; i
< node_nums
; i
++) {
976 devn
= CONFIG_CDB
+ i
;
978 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
982 pbus
= pci_domain
->link_list
->next
;
986 /* Find the cpu's pci device */
987 cdb_dev
= dev_find_slot(busn
, PCI_DEVFN(devn
, 0));
989 /* If I am probing things in a weird order
990 * ensure all of the cpu's pci devices are found.
993 for(fn
= 0; fn
<= 5; fn
++) { //FBDIMM?
994 cdb_dev
= pci_probe_dev(NULL
, pbus
,
995 PCI_DEVFN(devn
, fn
));
997 cdb_dev
= dev_find_slot(busn
, PCI_DEVFN(devn
, 0));
999 /* Ok, We need to set the links for that device.
1000 * otherwise the device under it will not be scanned
1003 #if CONFIG_HT3_SUPPORT
1008 add_more_links(cdb_dev
, linknum
);
1011 family
= cpuid_eax(1);
1012 family
= (family
>> 20) & 0xFF;
1013 if (family
== 1) { //f10
1015 cdb_dev
= dev_find_slot(busn
, PCI_DEVFN(devn
, 3));
1016 dword
= pci_read_config32(cdb_dev
, 0xe8);
1017 siblings
= ((dword
& BIT15
) >> 13) | ((dword
& (BIT13
| BIT12
)) >> 12);
1018 } else if (family
== 6) {//f15
1019 cdb_dev
= dev_find_slot(busn
, PCI_DEVFN(devn
, 5));
1020 if (cdb_dev
&& cdb_dev
->enabled
) {
1021 siblings
= pci_read_config32(cdb_dev
, 0x84);
1025 siblings
= 0; //default one core
1027 int enable_node
= cdb_dev
&& cdb_dev
->enabled
;
1028 printk(BIOS_SPEW
, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
1029 dev_path(cdb_dev
), 0x0f + family
, core_max
, core_nums
, siblings
);
1031 for (j
= 0; j
<= siblings
; j
++ ) {
1032 extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration
;
1033 u32 modules
= TopologyConfiguration
.PlatformNumberOfModules
;
1034 u32 lapicid_start
= 0;
1037 * APIC ID calucation is tightly coupled with AGESA v5 code.
1038 * This calculation MUST match the assignment calculation done
1039 * in LocalApicInitializationAtEarly() function.
1040 * And reference GetLocalApicIdForCore()
1042 * Apply apic enumeration rules
1043 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
1044 * put the local-APICs at m..z
1046 * This is needed because many IO-APIC devices only have 4 bits
1047 * for their APIC id and therefore must reside at 0..15
1049 #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
1050 #define CFG_PLAT_NUM_IO_APICS 3
1052 if ((node_nums
* core_max
) + CFG_PLAT_NUM_IO_APICS
>= 0x10) {
1053 lapicid_start
= (CFG_PLAT_NUM_IO_APICS
- 1) / core_max
;
1054 lapicid_start
= (lapicid_start
+ 1) * core_max
;
1055 printk(BIOS_SPEW
, "lpaicid_start=0x%x ", lapicid_start
);
1057 u32 apic_id
= (lapicid_start
* (i
/modules
+ 1)) + ((i
% modules
) ? (j
+ (siblings
+ 1)) : j
);
1058 printk(BIOS_SPEW
, "node 0x%x core 0x%x apicid=0x%x\n",
1061 device_t cpu
= add_cpu_device(cpu_bus
, apic_id
, enable_node
);
1063 amd_cpu_topology(cpu
, i
, j
);
1069 static void cpu_bus_init(device_t dev
)
1071 initialize_cpus(dev
->link_list
);
1074 static void cpu_bus_noop(device_t dev
)
1078 static void cpu_bus_read_resources(device_t dev
)
1080 #if CONFIG_MMCONF_SUPPORT
1081 struct resource
*resource
= new_resource(dev
, 0xc0010058);
1082 resource
->base
= CONFIG_MMCONF_BASE_ADDRESS
;
1083 resource
->size
= CONFIG_MMCONF_BUS_NUMBER
* 4096*256;
1084 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_RESERVE
|
1085 IORESOURCE_FIXED
| IORESOURCE_STORED
| IORESOURCE_ASSIGNED
;
1089 static void cpu_bus_set_resources(device_t dev
)
1091 struct resource
*resource
= find_resource(dev
, 0xc0010058);
1093 report_resource_stored(dev
, resource
, " <mmconfig>");
1095 pci_dev_set_resources(dev
);
1098 static struct device_operations cpu_bus_ops
= {
1099 .read_resources
= cpu_bus_read_resources
,
1100 .set_resources
= cpu_bus_set_resources
,
1101 .enable_resources
= cpu_bus_noop
,
1102 .init
= cpu_bus_init
,
1103 .scan_bus
= cpu_bus_scan
,
1106 static void root_complex_enable_dev(struct device
*dev
)
1108 static int done
= 0;
1110 /* Do not delay UMA setup, as a device on the PCI bus may evaluate
1111 the global uma_memory variables already in its enable function. */
1118 /* Set the operations if it is a special bus type */
1119 if (dev
->path
.type
== DEVICE_PATH_PCI_DOMAIN
) {
1120 dev
->ops
= &pci_domain_ops
;
1121 } else if (dev
->path
.type
== DEVICE_PATH_APIC_CLUSTER
) {
1122 dev
->ops
= &cpu_bus_ops
;
1126 struct chip_operations northbridge_amd_agesa_family15tn_root_complex_ops
= {
1127 CHIP_NAME("AMD FAM15 Root Complex")
1128 .enable_dev
= root_complex_enable_dev
,
1131 /********************************************************************
1132 * Change the vendor / device IDs to match the generic VBIOS header.
1133 ********************************************************************/
1134 u32
map_oprom_vendev(u32 vendev
)
1136 u32 new_vendev
=vendev
;
1139 //case 0x10029900: //FS1r2
1140 case 0x10029901: //FM2
1141 case 0x10029903: //FS1r2
1142 case 0x10029904: //FM2
1143 case 0x10029906: //FM2
1144 case 0x10029907: //FP2
1145 case 0x10029908: //FP2
1146 case 0x1002990A: //FP2
1147 case 0x10029910: //FS1r2
1148 case 0x10029913: //FS1r2
1149 case 0x10029917: //FP2
1150 case 0x10029918: //FP2
1151 case 0x10029919: //FP2
1152 case 0x10029990: //FS1r2
1153 case 0x10029991: //FM2
1154 case 0x10029992: //FS1r2
1155 case 0x10029993: //FM2
1156 case 0x10029994: //FP2
1157 case 0x100299A0: //FS1r2
1158 case 0x100299A2: //FS1r2
1159 case 0x100299A4: //FP2
1160 new_vendev
=0x10029900;