1 /* This is just an experiment. Full automatic porting
2 is probably not possible but a lot can be automated. */
21 type PCIDevData
struct {
28 type PCIDevice
interface {
29 Scan(ctx Context
, addr PCIDevData
)
32 type InteltoolData
struct {
33 GPIO
map[uint16]uint32
34 RCBA
map[uint16]uint32
45 type AzaliaCodec
struct {
50 PinConfig
map[int]uint32
53 type DevReader
interface {
54 GetPCIList() []PCIDevData
56 GetInteltool() InteltoolData
57 GetAzaliaCodecs() []AzaliaCodec
58 GetACPI() map[string][]byte
59 GetCPUModel() []uint32
61 GetIOPorts() []IOPorts
71 type SouthBridger
interface {
72 GetGPIOHeader() string
76 NeedRouteGPIOManually()
79 var SouthBridge SouthBridger
80 var ROMStageFiles
map[string]string = map[string]string{}
81 var RAMStageFiles
map[string]string = map[string]string{}
82 var SMMFiles
map[string]string = map[string]string{}
83 var MainboardInit
string
84 var MainboardEnable
string
85 var MainboardIncludes
[]string
97 type IOAPICIRQ
struct {
102 var IOAPICIRQs
map[PCIAddr
]IOAPICIRQ
= map[PCIAddr
]IOAPICIRQ
{}
103 var KconfigBool
map[string]bool = map[string]bool{}
104 var KconfigComment
map[string]string = map[string]string{}
105 var KconfigString
map[string]string = map[string]string{}
106 var KconfigStringUnquoted
map[string]string = map[string]string{}
107 var KconfigHex
map[string]uint32 = map[string]uint32{}
108 var KconfigInt
map[string]int = map[string]int{}
111 var FlashROMSupport
= ""
113 func GetLE16(inp
[]byte) uint16 {
114 return uint16(inp
[0]) |
(uint16(inp
[1]) << 8)
117 func FormatHexLE16(inp
[]byte) string {
118 return fmt
.Sprintf("0x%04x", GetLE16(inp
))
121 func FormatHex32(u
uint32) string {
122 return fmt
.Sprintf("0x%08x", u
)
125 func FormatHex8(u
uint8) string {
126 return fmt
.Sprintf("0x%02x", u
)
129 func FormatInt32(u
uint32) string {
130 return fmt
.Sprintf("%d", u
)
133 func FormatHexLE32(d
[]uint8) string {
134 u
:= uint32(d
[0]) |
(uint32(d
[1]) << 8) |
(uint32(d
[2]) << 16) |
(uint32(d
[3]) << 24)
135 return FormatHex32(u
)
138 func FormatBool(inp
bool) string {
146 func sanitize(inp
string) string {
147 result
:= strings
.ToLower(inp
)
148 result
= strings
.Replace(result
, " ", "_", -1)
149 result
= strings
.Replace(result
, ",", "_", -1)
150 for strings
.HasSuffix(result
, ".") {
151 result
= result
[0 : len(result
)-1]
156 func AddROMStageFile(Name
string, Condition
string) {
157 ROMStageFiles
[Name
] = Condition
160 func AddRAMStageFile(Name
string, Condition
string) {
161 RAMStageFiles
[Name
] = Condition
164 func AddSMMFile(Name
string, Condition
string) {
165 SMMFiles
[Name
] = Condition
168 func IsIOPortUsedBy(ctx Context
, port
uint16, name
string) bool {
169 for _
, io
:= range ctx
.InfoSource
.GetIOPorts() {
170 if io
.Start
<= port
&& port
<= io
.End
&& io
.Usage
== name
{
177 var FlagOutDir
= flag
.String("coreboot_dir", ".", "Resulting coreboot directory")
179 func writeMF(mf
*os
.File
, files
map[string]string, category
string) {
181 for file
, _
:= range files
{
182 keys
= append(keys
, file
)
187 for _
, file
:= range keys
{
188 condition
:= files
[file
]
190 fmt
.Fprintf(mf
, "%s-y += %s\n", category
, file
)
192 fmt
.Fprintf(mf
, "%s-$(%s) += %s\n", category
,
198 func Create(ctx Context
, name
string) *os
.File
{
199 li
:= strings
.LastIndex(name
, "/")
201 os
.MkdirAll(ctx
.BaseDirectory
+"/"+name
[0:li
], 0700)
203 mf
, err
:= os
.Create(ctx
.BaseDirectory
+ "/" + name
)
210 func RestorePCI16Simple(f
*os
.File
, pcidev PCIDevData
, addr
uint16) {
211 fmt
.Fprintf(f
, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n",
212 pcidev
.Bus
, pcidev
.Dev
, pcidev
.Func
, addr
,
213 pcidev
.ConfigDump
[addr
+1],
214 pcidev
.ConfigDump
[addr
])
217 func RestorePCI32Simple(f
*os
.File
, pcidev PCIDevData
, addr
uint16) {
218 fmt
.Fprintf(f
, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
219 pcidev
.Bus
, pcidev
.Dev
, pcidev
.Func
, addr
,
220 pcidev
.ConfigDump
[addr
+3],
221 pcidev
.ConfigDump
[addr
+2],
222 pcidev
.ConfigDump
[addr
+1],
223 pcidev
.ConfigDump
[addr
])
226 func RestoreRCBA32(f
*os
.File
, inteltool InteltoolData
, addr
uint16) {
227 fmt
.Fprintf(f
, "\tRCBA32(0x%04x) = 0x%08x;\n", addr
, inteltool
.RCBA
[addr
])
230 type PCISlot
struct {
232 additionalComment
string
236 type DevTreeNode
struct {
241 Registers
map[string]string
242 IOs
map[uint16]uint16
243 Children
[]DevTreeNode
254 var DevTree DevTreeNode
255 var MissingChildren
map[string][]DevTreeNode
= map[string][]DevTreeNode
{}
256 var unmatchedPCIChips
map[PCIAddr
]DevTreeNode
= map[PCIAddr
]DevTreeNode
{}
257 var unmatchedPCIDevices
map[PCIAddr
]DevTreeNode
= map[PCIAddr
]DevTreeNode
{}
259 func Offset(dt
*os
.File
, offset
int) {
260 for i
:= 0; i
< offset
; i
++ {
261 fmt
.Fprintf(dt
, "\t")
265 func MatchDev(dev
*DevTreeNode
) {
266 for idx
:= range dev
.Children
{
267 MatchDev(&dev
.Children
[idx
])
270 for _
, slot
:= range dev
.PCISlots
{
271 slotChip
, ok
:= unmatchedPCIChips
[slot
.PCIAddr
]
277 if slot
.additionalComment
!= "" && slotChip
.Comment
!= "" {
278 slotChip
.Comment
= slot
.additionalComment
+ " " + slotChip
.Comment
280 slotChip
.Comment
= slot
.additionalComment
+ slotChip
.Comment
283 delete(unmatchedPCIChips
, slot
.PCIAddr
)
285 dev
.Children
= append(dev
.Children
, slotChip
)
288 if dev
.PCIController
{
289 for slot
, slotDev
:= range unmatchedPCIChips
{
290 if slot
.Bus
== dev
.ChildPCIBus
{
291 delete(unmatchedPCIChips
, slot
)
293 dev
.Children
= append(dev
.Children
, slotDev
)
298 for _
, slot
:= range dev
.PCISlots
{
299 slotDev
, ok
:= unmatchedPCIDevices
[slot
.PCIAddr
]
302 dev
.Children
= append(dev
.Children
,
304 Registers
: map[string]string{},
309 Comment
: slot
.additionalComment
,
317 if slot
.additionalComment
!= "" && slotDev
.Comment
!= "" {
318 slotDev
.Comment
= slot
.additionalComment
+ " " + slotDev
.Comment
320 slotDev
.Comment
= slot
.additionalComment
+ slotDev
.Comment
324 dev
.Children
= append(dev
.Children
, slotDev
)
325 delete(unmatchedPCIDevices
, slot
.PCIAddr
)
328 if dev
.MissingParent
!= "" {
329 for _
, child
:= range MissingChildren
[dev
.MissingParent
] {
331 dev
.Children
= append(dev
.Children
, child
)
333 delete(MissingChildren
, dev
.MissingParent
)
336 if dev
.PCIController
{
337 for slot
, slotDev
:= range unmatchedPCIDevices
{
338 if slot
.Bus
== dev
.ChildPCIBus
{
340 dev
.Children
= append(dev
.Children
, slotDev
)
341 delete(unmatchedPCIDevices
, slot
)
347 func writeOn(dt
*os
.File
, dev DevTreeNode
) {
349 fmt
.Fprintf(dt
, "off")
351 fmt
.Fprintf(dt
, "on")
355 func WriteDev(dt
*os
.File
, offset
int, dev DevTreeNode
) {
358 case "cpu_cluster", "lapic", "domain", "ioapic":
359 fmt
.Fprintf(dt
, "device %s 0x%x ", dev
.Chip
, dev
.Dev
)
362 fmt
.Fprintf(dt
, "device %s %02x.%x ", dev
.Chip
, dev
.Dev
, dev
.Func
)
365 fmt
.Fprintf(dt
, "device %s %02x ", dev
.Chip
, dev
.Dev
)
368 fmt
.Fprintf(dt
, "chip %s", dev
.Chip
)
370 if dev
.Comment
!= "" {
371 fmt
.Fprintf(dt
, " # %s", dev
.Comment
)
373 fmt
.Fprintf(dt
, "\n")
374 if dev
.Chip
== "pci" && dev
.SubSystem
!= 0 && dev
.SubVendor
!= 0 {
376 fmt
.Fprintf(dt
, "subsystemid 0x%04x 0x%04x\n", dev
.SubVendor
, dev
.SubSystem
)
379 ioapic
, ok
:= IOAPICIRQs
[PCIAddr
{Bus
: dev
.Bus
, Dev
: dev
.Dev
, Func
: dev
.Func
}]
380 if dev
.Chip
== "pci" && ok
{
381 for pin
, irq
:= range ioapic
.IRQNO
{
384 fmt
.Fprintf(dt
, "ioapic_irq %d INT%c 0x%x\n", ioapic
.APICID
, 'A'+pin
, irq
)
390 for reg
, _
:= range dev
.Registers
{
391 keys
= append(keys
, reg
)
396 for _
, reg
:= range keys
{
397 val
:= dev
.Registers
[reg
]
399 fmt
.Fprintf(dt
, "register \"%s\" = \"%s\"\n", reg
, val
)
403 for reg
, _
:= range dev
.IOs
{
404 ios
= append(ios
, int(reg
))
409 for _
, reg
:= range ios
{
410 val
:= dev
.IOs
[uint16(reg
)]
412 fmt
.Fprintf(dt
, "io 0x%x = 0x%x\n", reg
, val
)
415 for _
, child
:= range dev
.Children
{
416 WriteDev(dt
, offset
+1, child
)
420 fmt
.Fprintf(dt
, "end\n")
423 func PutChip(domain
string, cur DevTreeNode
) {
424 MissingChildren
[domain
] = append(MissingChildren
[domain
], cur
)
427 func PutPCIChip(addr PCIDevData
, cur DevTreeNode
) {
428 unmatchedPCIChips
[addr
.PCIAddr
] = cur
431 func PutPCIDevParent(addr PCIDevData
, comment
string, parent
string) {
433 Registers
: map[string]string{},
438 MissingParent
: parent
,
441 if addr
.ConfigDump
[0xa] == 0x04 && addr
.ConfigDump
[0xb] == 0x06 {
442 cur
.PCIController
= true
443 cur
.ChildPCIBus
= int(addr
.ConfigDump
[0x19])
446 for capPtr
:= addr
.ConfigDump
[0x34]; capPtr
!= 0; capPtr
= addr
.ConfigDump
[capPtr
+1] {
447 /* Avoid hangs. There are only 0x100 different possible values for capPtr.
448 If we iterate longer than that, we're in endless loop. */
453 if addr
.ConfigDump
[capPtr
] == 0x0d {
454 cur
.SubVendor
= GetLE16(addr
.ConfigDump
[capPtr
+4 : capPtr
+6])
455 cur
.SubSystem
= GetLE16(addr
.ConfigDump
[capPtr
+6 : capPtr
+8])
459 cur
.SubVendor
= GetLE16(addr
.ConfigDump
[0x2c:0x2e])
460 cur
.SubSystem
= GetLE16(addr
.ConfigDump
[0x2e:0x30])
462 unmatchedPCIDevices
[addr
.PCIAddr
] = cur
465 func PutPCIDev(addr PCIDevData
, comment
string) {
466 PutPCIDevParent(addr
, comment
, "")
469 type GenericPCI
struct {
475 type GenericVGA
struct {
479 type DSDTInclude
struct {
484 type DSDTDefine
struct {
490 var DSDTIncludes
[]DSDTInclude
491 var DSDTPCI0Includes
[]DSDTInclude
492 var DSDTDefines
[]DSDTDefine
494 func (g GenericPCI
) Scan(ctx Context
, addr PCIDevData
) {
495 PutPCIDevParent(addr
, g
.Comment
, g
.MissingParent
)
498 func (g GenericVGA
) Scan(ctx Context
, addr PCIDevData
) {
499 KconfigString
["VGA_BIOS_ID"] = fmt
.Sprintf("%04x,%04x",
502 KconfigString
["VGA_BIOS_FILE"] = fmt
.Sprintf("pci%04x,%04x.rom",
505 PutPCIDevParent(addr
, g
.Comment
, g
.MissingParent
)
508 func makeKconfigName(ctx Context
) {
509 kn
:= Create(ctx
, "Kconfig.name")
512 fmt
.Fprintf(kn
, "config %s\n\tbool \"%s\"\n", ctx
.KconfigName
, ctx
.Model
)
515 func makeComment(name
string) string {
516 cmt
, ok
:= KconfigComment
[name
]
523 func makeKconfig(ctx Context
) {
524 kc
:= Create(ctx
, "Kconfig")
527 fmt
.Fprintf(kc
, "if %s\n\n", ctx
.KconfigName
)
529 fmt
.Fprintf(kc
, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n")
531 for name
, val
:= range KconfigBool
{
533 keys
= append(keys
, name
)
539 for _
, name
:= range keys
{
540 fmt
.Fprintf(kc
, "\tselect %s%s\n", name
, makeComment(name
))
544 for name
, val
:= range KconfigBool
{
546 keys
= append(keys
, name
)
552 for _
, name
:= range keys
{
557 `, name
, makeComment(name
))
561 for name
, _
:= range KconfigStringUnquoted
{
562 keys
= append(keys
, name
)
567 for _
, name
:= range keys
{
572 `, name
, makeComment(name
), KconfigStringUnquoted
[name
])
576 for name
, _
:= range KconfigString
{
577 keys
= append(keys
, name
)
582 for _
, name
:= range keys
{
587 `, name
, makeComment(name
), KconfigString
[name
])
591 for name
, _
:= range KconfigHex
{
592 keys
= append(keys
, name
)
597 for _
, name
:= range keys
{
602 `, name
, makeComment(name
), KconfigHex
[name
])
606 for name
, _
:= range KconfigInt
{
607 keys
= append(keys
, name
)
612 for _
, name
:= range keys
{
617 `, name
, makeComment(name
), KconfigInt
[name
])
620 fmt
.Fprintf(kc
, "endif\n")
623 const MoboDir
= "/src/mainboard/"
625 func makeVendor(ctx Context
) {
627 vendorSane
:= ctx
.SaneVendor
628 vendorDir
:= *FlagOutDir
+ MoboDir
+ vendorSane
629 vendorUpper
:= strings
.ToUpper(vendorSane
)
630 kconfig
:= vendorDir
+ "/Kconfig"
631 if _
, err
:= os
.Stat(kconfig
); os
.IsNotExist(err
) {
632 f
, err
:= os
.Create(kconfig
)
637 f
.WriteString(`if VENDOR_` + vendorUpper
+ `
640 prompt "Mainboard model"
642 source "src/mainboard/` + vendorSane
+ `/*/Kconfig.name"
646 source "src/mainboard/` + vendorSane
+ `/*/Kconfig"
648 config MAINBOARD_VENDOR
650 default "` + vendor
+ `"
652 endif # VENDOR_` + vendorUpper
+ "\n")
654 kconfigName
:= vendorDir
+ "/Kconfig.name"
655 if _
, err
:= os
.Stat(kconfigName
); os
.IsNotExist(err
) {
656 f
, err
:= os
.Create(kconfigName
)
661 f
.WriteString(`config VENDOR_` + vendorUpper
+ `
662 bool "` + vendor
+ `"
668 func GuessECGPE(ctx Context
) int {
669 /* FIXME:XX Use iasl -d and/or better parsing */
670 dsdt
:= ctx
.InfoSource
.GetACPI()["DSDT"]
671 idx
:= bytes
.Index(dsdt
, []byte{0x08, '_', 'G', 'P', 'E', 0x0a}) /* Name (_GPE, byte). */
673 return int(dsdt
[idx
+6])
678 func GuessSPDMap(ctx Context
) []uint8 {
679 dmi
:= ctx
.InfoSource
.GetDMI()
681 if dmi
.Vendor
== "LENOVO" {
682 return []uint8{0x50, 0x52, 0x51, 0x53}
684 return []uint8{0x50, 0x51, 0x52, 0x53}
692 ctx
.InfoSource
= MakeLogReader()
694 dmi
:= ctx
.InfoSource
.GetDMI()
696 ctx
.Vendor
= dmi
.Vendor
698 if dmi
.Vendor
== "LENOVO" {
699 ctx
.Model
= dmi
.Version
701 ctx
.Model
= dmi
.Model
705 KconfigBool
["SYSTEM_TYPE_LAPTOP"] = true
707 ctx
.SaneVendor
= sanitize(ctx
.Vendor
)
709 last
:= ctx
.SaneVendor
710 for _
, suf
:= range []string{"_inc", "_co", "_corp"} {
711 ctx
.SaneVendor
= strings
.TrimSuffix(ctx
.SaneVendor
, suf
)
713 if last
== ctx
.SaneVendor
{
717 ctx
.MoboID
= ctx
.SaneVendor
+ "/" + sanitize(ctx
.Model
)
718 ctx
.KconfigName
= "BOARD_" + strings
.ToUpper(ctx
.SaneVendor
+"_"+sanitize(ctx
.Model
))
719 ctx
.BaseDirectory
= *FlagOutDir
+ MoboDir
+ ctx
.MoboID
720 KconfigStringUnquoted
["MAINBOARD_DIR"] = ctx
.MoboID
721 KconfigString
["MAINBOARD_PART_NUMBER"] = ctx
.Model
723 os
.MkdirAll(ctx
.BaseDirectory
, 0700)
729 if len(ROMStageFiles
) > 0 ||
len(RAMStageFiles
) > 0 ||
len(SMMFiles
) > 0 {
730 mf
:= Create(ctx
, "Makefile.inc")
732 writeMF(mf
, ROMStageFiles
, "romstage")
733 writeMF(mf
, RAMStageFiles
, "ramstage")
734 writeMF(mf
, SMMFiles
, "smm")
737 devtree
:= Create(ctx
, "devicetree.cb")
738 defer devtree
.Close()
741 WriteDev(devtree
, 0, DevTree
)
743 if MainboardInit
!= "" || MainboardEnable
!= "" || MainboardIncludes
!= nil {
744 mainboard
:= Create(ctx
, "mainboard.c")
745 defer mainboard
.Close()
746 mainboard
.WriteString("#include <device/device.h>\n")
747 for _
, include
:= range MainboardIncludes
{
748 mainboard
.WriteString("#include <" + include
+ ">\n")
750 mainboard
.WriteString("\n")
751 if MainboardInit
!= "" {
752 mainboard
.WriteString(`static void mainboard_init(device_t dev)
754 ` + MainboardInit
+ "}\n\n")
756 if MainboardInit
!= "" || MainboardEnable
!= "" {
757 mainboard
.WriteString("static void mainboard_enable(device_t dev)\n{\n")
758 if MainboardInit
!= "" {
759 mainboard
.WriteString("\tdev->ops->init = mainboard_init;\n\n")
761 mainboard
.WriteString(MainboardEnable
)
762 mainboard
.WriteString("}\n\n")
763 mainboard
.WriteString(`struct chip_operations mainboard_ops = {
764 .enable_dev = mainboard_enable,
770 at
:= Create(ctx
, "acpi_tables.c")
772 at
.WriteString("/* dummy */\n")
774 bi
:= Create(ctx
, "board_info.txt")
780 bi
.WriteString("Category: laptop\n")
782 bi
.WriteString("Category: desktop\n")
783 fixme
+= "check category, "
786 missing
:= "ROM package, ROM socketed"
788 if ROMProtocol
!= "" {
789 fmt
.Fprintf(bi
, "ROM protocol: %s\n", ROMProtocol
)
791 missing
+= ", ROM protocol"
794 if FlashROMSupport
!= "" {
795 fmt
.Fprintf(bi
, "Flashrom support: %s\n", FlashROMSupport
)
797 missing
+= ", Flashrom support"
800 missing
+= ", Release year"
803 fmt
.Fprintf(bi
, "FIXME: %s, put %s\n", fixme
, missing
)
805 fmt
.Fprintf(bi
, "FIXME: put %s\n", missing
)
808 rs
:= Create(ctx
, "romstage.c")
810 rs
.WriteString("/* dummy file */\n")
813 KconfigBool
["BOARD_ROMSIZE_KB_2048"] = true
814 KconfigComment
["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
816 KconfigBool
[fmt
.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB
)] = true
822 dsdt
:= Create(ctx
, "dsdt.asl")
825 for _
, define
:= range DSDTDefines
{
826 if define
.Comment
!= "" {
827 fmt
.Fprintf(dsdt
, "\t/* %s. */\n", define
.Comment
)
829 dsdt
.WriteString("#define " + define
.Key
+ " " + define
.Value
+ "\n")
836 0x03, // DSDT revision: ACPI v3.0
838 "COREBOOT", // OEM table id
839 0x20141018 // OEM revision
842 // Some generic macros
843 #include "acpi/platform.asl"
846 for _
, x
:= range DSDTIncludes
{
848 fmt
.Fprintf(dsdt
, "\t/* %s. */\n", x
.Comment
)
850 fmt
.Fprintf(dsdt
, "\t#include <%s>\n", x
.File
)
858 for _
, x
:= range DSDTPCI0Includes
{
860 fmt
.Fprintf(dsdt
, "\t/* %s. */\n", x
.Comment
)
862 fmt
.Fprintf(dsdt
, "\t\t#include <%s>\n", x
.File
)