src/mainboard/google/fizz/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "1"
   7         register "deep_s5_enable_dc" = "1"
   8         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
   9
  10         # Mapping of USB port # to device
  11         #+----------------+-------+-----------------------------------+
  12         #| Device         | Port# | Rev                               |
  13         #+----------------+-------+-----------------------------------+
  14         #| USB C          |   1   | 2/3                               |
  15         #| USB A Rear     |   2   | 2/3                               |
  16         #| USB A Front    |   3   | 2/3                               |
  17         #| USB A Front    |   4   | 2/3                               |
  18         #| USB A Rear     |   5   | 2 on base celeron, 2/3 all others |
  19         #| USB A Rear     |   6   | 2 on base celeron, 2/3 all others |
  20         #| Bluetooth      |   7   |                                   |
  21         #| Daughter Board |   8   |                                   |
  22         #+----------------+-------+-----------------------------------+
  23
  24         # Bitmap for Wake Enable on USB attach/detach
  25         register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
  26                                               USB_PORT_WAKE_ENABLE(3) | \
  27                                               USB_PORT_WAKE_ENABLE(4) | \
  28                                               USB_PORT_WAKE_ENABLE(5) | \
  29                                               USB_PORT_WAKE_ENABLE(6)"
  30         register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
  31                                               USB_PORT_WAKE_ENABLE(3) | \
  32                                               USB_PORT_WAKE_ENABLE(4) | \
  33                                               USB_PORT_WAKE_ENABLE(5) | \
  34                                               USB_PORT_WAKE_ENABLE(6)"
  35
  36         # GPE configuration
  37         # Note that GPE events called out in ASL code rely on this
  38         # route. i.e. If this route changes then the affected GPE
  39         # offset bits also need to be changed.
  40         register "gpe0_dw0" = "GPP_B"
  41         register "gpe0_dw1" = "GPP_D"
  42         register "gpe0_dw2" = "GPP_E"
  43
  44         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  45         register "gen1_dec" = "0x00fc0801"
  46         register "gen2_dec" = "0x000c0201"
  47         # EC memory map range is 0x900-0x9ff
  48         register "gen3_dec" = "0x00fc0901"
  49
  50         # Enable DPTF
  51         register "dptf_enable" = "1"
  52
  53         # Enable S0ix
  54         register "s0ix_enable" = "1"
  55
  56         # FSP Configuration
  57         register "ProbelessTrace" = "0"
  58         register "EnableLan" = "0"
  59         register "EnableSata" = "1"
  60         register "SataSalpSupport" = "0"
  61         register "SataMode" = "0"
  62         register "SataPortsEnable[0]" = "1"
  63         register "SataPortsEnable[1]" = "1"
  64         register "SataPortsDevSlp[1]" = "1"
  65         register "SataPwrOptEnable" = "1"
  66         register "EnableAzalia" = "1"
  67         register "DspEnable" = "1"
  68         register "IoBufferOwnership" = "3"
  69         register "EnableTraceHub" = "0"
  70         register "SsicPortEnable" = "0"
  71         register "SmbusEnable" = "1"
  72         register "Cio2Enable" = "0"
  73         register "ScsEmmcEnabled" = "0"
  74         register "ScsEmmcHs400Enabled" = "0"
  75         register "ScsSdCardEnabled" = "2"
  76         register "IshEnable" = "0"
  77         register "PttSwitch" = "0"
  78         register "InternalGfx" = "1"
  79         register "SkipExtGfxScan" = "1"
  80         register "Device4Enable" = "1"
  81         register "HeciEnabled" = "0"
  82         register "FspSkipMpInit" = "1"
  83         register "SaGv" = "3"
  84         register "SerialIrqConfigSirqEnable" = "1"
  85         register "PmConfigSlpS3MinAssert" = "2"        # 50ms
  86         register "PmConfigSlpS4MinAssert" = "1"        # 1s
  87         register "PmConfigSlpSusMinAssert" = "1"       # 500ms
  88         register "PmConfigSlpAMinAssert" = "3"         # 2s
  89         register "PmTimerDisabled" = "1"
  90         register "SendVrMbxCmd" = "1"                  # IMVP8 workaround
  91         register "VmxEnable" = "1"
  92
  93         # Intersil VR c-state issue workaround
  94         # send VR mailbox command for IA/GT/SA rails
  95         register "IslVrCmd" = "2"
  96
  97         register "pirqa_routing" = "PCH_IRQ11"
  98         register "pirqb_routing" = "PCH_IRQ10"
  99         register "pirqc_routing" = "PCH_IRQ11"
 100         register "pirqd_routing" = "PCH_IRQ11"
 101         register "pirqe_routing" = "PCH_IRQ11"
 102         register "pirqf_routing" = "PCH_IRQ11"
 103         register "pirqg_routing" = "PCH_IRQ11"
 104         register "pirqh_routing" = "PCH_IRQ11"
 105
 106         # VR Settings Configuration for 4 Domains
 107         #+----------------+-------+-------+-------+-------+
 108         #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
 109         #+----------------+-------+-------+-------+-------+
 110         #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
 111         #| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
 112         #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
 113         #| Psi3Enable     | 1     | 1     | 1     | 1     |
 114         #| Psi4Enable     | 1     | 1     | 1     | 1     |
 115         #| ImonSlope      | 0     | 0     | 0     | 0     |
 116         #| ImonOffset     | 0     | 0     | 0     | 0     |
 117         #| IccMax         | 7A    | 34A   | 35A   | 35A   |
 118         #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
 119         #| AcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
 120         #| DcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
 121         #+----------------+-------+-------+-------+-------+
 122         #Note: IccMax settings are moved to SoC code
 123         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 124                 .vr_config_enable = 1,
 125                 .psi1threshold = VR_CFG_AMP(20),
 126                 .psi2threshold = VR_CFG_AMP(4),
 127                 .psi3threshold = VR_CFG_AMP(1),
 128                 .psi3enable = 1,
 129                 .psi4enable = 1,
 130                 .imon_slope = 0x0,
 131                 .imon_offset = 0x0,
 132                 .voltage_limit = 1520,
 133                 .ac_loadline = 1030,
 134                 .dc_loadline = 1030,
 135         }"
 136
 137         register "domain_vr_config[VR_IA_CORE]" = "{
 138                 .vr_config_enable = 1,
 139                 .psi1threshold = VR_CFG_AMP(20),
 140                 .psi2threshold = VR_CFG_AMP(5),
 141                 .psi3threshold = VR_CFG_AMP(1),
 142                 .psi3enable = 1,
 143                 .psi4enable = 1,
 144                 .imon_slope = 0x0,
 145                 .imon_offset = 0x0,
 146                 .voltage_limit = 1520,
 147                 .ac_loadline = 240,
 148                 .dc_loadline = 240,
 149         }"
 150
 151         register "domain_vr_config[VR_GT_UNSLICED]" = "{
 152                 .vr_config_enable = 1,
 153                 .psi1threshold = VR_CFG_AMP(20),
 154                 .psi2threshold = VR_CFG_AMP(5),
 155                 .psi3threshold = VR_CFG_AMP(1),
 156                 .psi3enable = 1,
 157                 .psi4enable = 1,
 158                 .imon_slope = 0x0,
 159                 .imon_offset = 0x0,
 160                 .voltage_limit = 1520,
 161                 .ac_loadline = 310,
 162                 .dc_loadline = 310,
 163         }"
 164
 165         register "domain_vr_config[VR_GT_SLICED]" = "{
 166                 .vr_config_enable = 1,
 167                 .psi1threshold = VR_CFG_AMP(20),
 168                 .psi2threshold = VR_CFG_AMP(5),
 169                 .psi3threshold = VR_CFG_AMP(1),
 170                 .psi3enable = 1,
 171                 .psi4enable = 1,
 172                 .imon_slope = 0x0,
 173                 .imon_offset = 0x0,
 174                 .voltage_limit = 1520,
 175                 .ac_loadline = 310,
 176                 .dc_loadline = 310,
 177         }"
 178
 179         # Enable Root port 3(x1) for LAN.
 180         register "PcieRpEnable[2]" = "1"
 181         # Enable CLKREQ#
 182         register "PcieRpClkReqSupport[2]" = "1"
 183         # RP 3 uses SRCCLKREQ0#
 184         register "PcieRpClkReqNumber[2]" = "0"
 185         # RP 3, Enable Advanced Error Reporting
 186         register "PcieRpAdvancedErrorReporting[2]" = "1"
 187         # RP 3, Enable Latency Tolerance Reporting Mechanism
 188         register "PcieRpLtrEnable[2]" = "1"
 189         # RP 3 uses uses CLK SRC 0
 190         register "PcieRpClkSrcNumber[2]" = "0"
 191
 192         # Enable Root port 4(x1) for WLAN.
 193         register "PcieRpEnable[3]" = "1"
 194         # Enable CLKREQ#
 195         register "PcieRpClkReqSupport[3]" = "1"
 196         # RP 4 uses SRCCLKREQ5#
 197         register "PcieRpClkReqNumber[3]" = "5"
 198         # RP 4, Enable Advanced Error Reporting
 199         register "PcieRpAdvancedErrorReporting[3]" = "1"
 200         # RP 4, Enable Latency Tolerance Reporting Mechanism
 201         register "PcieRpLtrEnable[3]" = "1"
 202         # RP 4 uses uses CLK SRC 5
 203         register "PcieRpClkSrcNumber[3]" = "5"
 204
 205         # Enable Root port 5(x4) for NVMe.
 206         register "PcieRpEnable[4]" = "1"
 207         # Enable CLKREQ#
 208         register "PcieRpClkReqSupport[4]" = "1"
 209         # RP 5 uses SRCCLKREQ1#
 210         register "PcieRpClkReqNumber[4]" = "1"
 211         # RP 5, Enable Advanced Error Reporting
 212         register "PcieRpAdvancedErrorReporting[4]" = "1"
 213         # RP 5, Enable Latency Tolerance Reporting Mechanism
 214         register "PcieRpLtrEnable[4]" = "1"
 215         # RP 5 uses CLK SRC 1
 216         register "PcieRpClkSrcNumber[4]" = "1"
 217
 218         # Enable Root port 9 for BtoB.
 219         register "PcieRpEnable[8]" = "1"
 220         # Enable CLKREQ#
 221         register "PcieRpClkReqSupport[8]" = "1"
 222         # RP 9 uses SRCCLKREQ2#
 223         register "PcieRpClkReqNumber[8]" = "2"
 224         # RP 9, Enable Advanced Error Reporting
 225         register "PcieRpAdvancedErrorReporting[8]" = "1"
 226         # RP 9, Enable Latency Tolerance Reporting Mechanism
 227         register "PcieRpLtrEnable[8]" = "1"
 228         # RP 9 uses uses CLK SRC 2
 229         register "PcieRpClkSrcNumber[8]" = "2"
 230
 231         # Enable Root port 11 for BtoB.
 232         register "PcieRpEnable[10]" = "1"
 233         # Enable CLKREQ#
 234         register "PcieRpClkReqSupport[10]" = "1"
 235         # RP 11 uses SRCCLKREQ2#
 236         register "PcieRpClkReqNumber[10]" = "2"
 237         # RP 11, Enable Advanced Error Reporting
 238         register "PcieRpAdvancedErrorReporting[10]" = "1"
 239         # RP 11, Enable Latency Tolerance Reporting Mechanism
 240         register "PcieRpLtrEnable[10]" = "1"
 241         # RP 11 uses uses CLK SRC 2
 242         register "PcieRpClkSrcNumber[10]" = "2"
 243
 244         # Enable Root port 12 for BtoB.
 245         register "PcieRpEnable[11]" = "1"
 246         # Enable CLKREQ#
 247         register "PcieRpClkReqSupport[11]" = "1"
 248         # RP 12 uses SRCCLKREQ2#
 249         register "PcieRpClkReqNumber[11]" = "2"
 250         # RP 12, Enable Advanced Error Reporting
 251         register "PcieRpAdvancedErrorReporting[11]" = "1"
 252         # RP 12, Enable Latency Tolerance Reporting Mechanism
 253         register "PcieRpLtrEnable[11]" = "1"
 254         # RP 12 uses uses CLK SRC 2
 255         register "PcieRpClkSrcNumber[11]" = "2"
 256
 257         register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"        # Type-C
 258         register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"         # Type-A Rear
 259         register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"         # Type-A Front
 260         register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"         # Type-A Front
 261         register "usb2_ports[4]" = "USB2_PORT_MID(OC1)"         # Type-A Rear
 262         register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"         # Type-A Rear
 263         register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth
 264         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A 2.0 / Debug
 265         register "usb2_ports[8]" = "USB2_PORT_EMPTY"            # H1 (disconnected)
 266
 267         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"     # Type-C
 268         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"     # Type-A Rear
 269         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"     # Type-A Front
 270         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"     # Type-A Front
 271         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Rear
 272         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Rear
 273
 274         register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"           # HDMI CEC
 275         register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"           # TPM
 276         register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3"           # Debug
 277         register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"           # Audio
 278
 279         # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
 280         # communication before memory is up.
 281         register "gspi[0]" = "{
 282                  .speed_mhz = 1,
 283                  .early_init = 1,
 284         }"
 285
 286         # audio
 287         register "i2c[5]" = "{
 288                  .speed = I2C_SPEED_FAST,
 289                  .speed_config[0] = {
 290                         .speed = I2C_SPEED_FAST,
 291                         .scl_lcnt = 194,
 292                         .scl_hcnt = 100,
 293                         .sda_hold = 36,
 294                 },
 295         }"
 296
 297         # Must leave UART0 enabled or SD/eMMC will not work as PCI
 298         register "SerialIoDevMode" = "{
 299                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
 300                 [PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
 301                 [PchSerialIoIndexI2C2]  = PchSerialIoPci,
 302                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 303                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 304                 [PchSerialIoIndexI2C5]  = PchSerialIoPci,
 305                 [PchSerialIoIndexSpi0]  = PchSerialIoPci,
 306                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
 307                 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
 308                 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
 309                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 310         }"
 311
 312         register "speed_shift_enable" = "1"
 313         register "tdp_psyspl2" = "90"
 314         register "psys_pmax" = "120"
 315         register "tcc_offset" = "6"     # TCC of 94C
 316
 317         # Use default SD card detect GPIO configuration
 318         register "sdcard_cd_gpio_default" = "GPP_A7"
 319
 320         # Lock Down
 321         register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
 322
 323         device cpu_cluster 0 on
 324                 device lapic 0 on end
 325         end
 326         device domain 0 on
 327                 device pci 00.0 on  end # Host Bridge
 328                 device pci 02.0 on  end # Integrated Graphics Device
 329                 device pci 14.0 on
 330                         chip drivers/usb/acpi
 331                                 register "desc" = ""Root Hub""
 332                                 register "type" = "UPC_TYPE_HUB"
 333                                 device usb 0.0 on
 334                                         chip drivers/usb/acpi
 335                                                 register "desc" = ""USB2 Type-C Rear""
 336                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 337                                                 device usb 2.0 on end
 338                                         end
 339                                         chip drivers/usb/acpi
 340                                                 register "desc" = ""USB2 Type-A Rear Left""
 341                                                 register "type" = "UPC_TYPE_A"
 342                                                 device usb 2.1 on end
 343                                         end
 344                                         chip drivers/usb/acpi
 345                                                 register "desc" = ""USB2 Type-A Front Right""
 346                                                 register "type" = "UPC_TYPE_A"
 347                                                 device usb 2.2 on end
 348                                         end
 349                                         chip drivers/usb/acpi
 350                                                 register "desc" = ""USB2 Type-A Front Left""
 351                                                 register "type" = "UPC_TYPE_A"
 352                                                 device usb 2.3 on end
 353                                         end
 354                                         chip drivers/usb/acpi
 355                                                 register "desc" = ""USB2 Type-A Rear Right""
 356                                                 register "type" = "UPC_TYPE_A"
 357                                                 device usb 2.4 on end
 358                                         end
 359                                         chip drivers/usb/acpi
 360                                                 register "desc" = ""USB2 Type-A Rear Middle""
 361                                                 register "type" = "UPC_TYPE_A"
 362                                                 device usb 2.5 on end
 363                                         end
 364                                         chip drivers/usb/acpi
 365                                                 register "desc" = ""USB2 Bluetooth""
 366                                                 register "type" = "UPC_TYPE_INTERNAL"
 367                                                 device usb 2.6 on end
 368                                         end
 369                                         chip drivers/usb/acpi
 370                                                 register "desc" = ""USB3 Type-C Rear""
 371                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 372                                                 device usb 3.0 on end
 373                                         end
 374                                         chip drivers/usb/acpi
 375                                                 register "desc" = ""USB3 Type-A Rear Left""
 376                                                 register "type" = "UPC_TYPE_USB3_A"
 377                                                 device usb 3.1 on end
 378                                         end
 379                                         chip drivers/usb/acpi
 380                                                 register "desc" = ""USB3 Type-A Front Right""
 381                                                 register "type" = "UPC_TYPE_USB3_A"
 382                                                 device usb 3.2 on end
 383                                         end
 384                                         chip drivers/usb/acpi
 385                                                 register "desc" = ""USB3 Type-A Front Left""
 386                                                 register "type" = "UPC_TYPE_USB3_A"
 387                                                 device usb 3.3 on end
 388                                         end
 389                                         chip drivers/usb/acpi
 390                                                 register "desc" = ""USB3 Type-A Rear Right""
 391                                                 register "type" = "UPC_TYPE_USB3_A"
 392                                                 device usb 3.4 on end
 393                                         end
 394                                         chip drivers/usb/acpi
 395                                                 register "desc" = ""USB3 Type-A Rear Middle""
 396                                                 register "type" = "UPC_TYPE_USB3_A"
 397                                                 device usb 3.5 on end
 398                                         end
 399                                 end
 400                         end
 401                 end # USB xHCI
 402                 device pci 14.1 off end # USB xDCI (OTG)
 403                 device pci 14.2 on  end # Thermal Subsystem
 404                 device pci 15.0 on  end # I2C #0
 405                 device pci 15.1 off end # I2C #1
 406                 device pci 15.2 on  end # I2C #2
 407                 device pci 15.3 off end # I2C #3
 408                 device pci 16.0 on  end # Management Engine Interface 1
 409                 device pci 16.1 off end # Management Engine Interface 2
 410                 device pci 16.2 off end # Management Engine IDE-R
 411                 device pci 16.3 off end # Management Engine KT Redirection
 412                 device pci 16.4 off end # Management Engine Interface 3
 413                 device pci 17.0 on end # SATA
 414                 device pci 19.0 on  end # UART #2
 415                 device pci 19.1 on
 416                         chip drivers/i2c/generic
 417                                 register "hid" = ""10EC5663""
 418                                 register "name" = ""RT53""
 419                                 register "desc" = ""Realtek RT5663""
 420                                 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
 421                                 device i2c 13 on end
 422                         end
 423                 end # I2C #5
 424                 device pci 19.2 off  end # I2C #4
 425                 device pci 1c.0 on # PCI Express Port 1
 426                         chip drivers/net
 427                                 register "customized_leds" = "0x0fa5"
 428                                 register "wake" = "GPE0_PCI_EXP"
 429                                 register "device_index" = "1"
 430                                 device pci 00.0 on end
 431                         end
 432                 end # PCI Express Port 1
 433                 device pci 1c.1 off end # PCI Express Port 2
 434                 # PCI Express Port 3 for LAN, but will be swapped to port 1
 435                 device pci 1c.2 on end
 436                 device pci 1c.3 on
 437                         chip drivers/intel/wifi
 438                                 register "wake" = "GPE0_PCI_EXP"
 439                                 device pci 00.0 on end
 440                         end
 441                 end # PCI Express Port 4 for WLAN
 442                 device pci 1c.4 on end # PCI Express Port 5 for NVMe
 443                 device pci 1c.5 off end # PCI Express Port 6
 444                 device pci 1c.6 off end # PCI Express Port 7
 445                 device pci 1c.7 off end # PCI Express Port 8
 446                 device pci 1d.0 on # PCI Express Port 9 for 2nd LAN
 447                         chip drivers/net
 448                                 register "customized_leds" = "0x0fa5"
 449                                 register "device_index" = "2"
 450                                 device pci 00.0 on end
 451                         end
 452                 end # PCI Express Port 9 for BtoB
 453                 device pci 1d.1 off end # PCI Express Port 10
 454                 device pci 1d.2 on end # PCI Express Port 11
 455                 device pci 1d.3 on end # PCI Express Port 12
 456                 device pci 1e.0 on  end # UART #0
 457                 device pci 1e.1 off end # UART #1
 458                 device pci 1e.2 on
 459                         chip drivers/spi/acpi
 460                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 461                                 register "compat_string" = ""google,cr50""
 462                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
 463                                 device spi 0 on end
 464                         end
 465                 end # GSPI #0
 466                 device pci 1e.3 off end # GSPI #1
 467                 device pci 1e.4 off  end # eMMC
 468                 device pci 1e.5 off end # SDIO
 469                 device pci 1e.6 on end # SDCard
 470                 device pci 1f.0 on
 471                         chip ec/google/chromeec
 472                                 device pnp 0c09.0 on end
 473                         end
 474                 end # LPC Interface
 475                 device pci 1f.1 on  end # P2SB
 476                 device pci 1f.2 on  end # Power Management Controller
 477                 device pci 1f.3 on  end # Intel HDA
 478                 device pci 1f.4 on  end # SMBus
 479                 device pci 1f.5 on  end # PCH SPI
 480                 device pci 1f.6 off end # GbE
 481         end
 482 end