mb/google/auron: Move SPD file handling to chipset
[coreboot.git] / src / mainboard / google / auron / chromeos.c
blob84940e2f5cbd04b9d3685e7a6bfd3be375e493e2
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootmode.h>
4 #include <boot/coreboot_tables.h>
5 #include <types.h>
6 #include <vendorcode/google/chromeos/chromeos.h>
7 #include <soc/chromeos.h>
8 #include <southbridge/intel/lynxpoint/lp_gpio.h>
10 #include "onboard.h"
12 /* EC_IN_RW is GPIO 25 in samus and 14 otherwise */
13 #if CONFIG(BOARD_GOOGLE_SAMUS)
14 #define EC_IN_RW_GPIO 25
15 #else
16 #define EC_IN_RW_GPIO 14
17 #endif
19 void fill_lb_gpios(struct lb_gpios *gpios)
21 struct lb_gpio chromeos_gpios[] = {
22 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
23 {-1, ACTIVE_HIGH, 0, "power"},
24 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
26 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
29 int get_write_protect_state(void)
31 return get_gpio(CROS_WP_GPIO);
34 static const struct cros_gpio cros_gpios[] = {
35 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
36 CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
38 DECLARE_CROS_GPIOS(cros_gpios);
40 int get_ec_is_trusted(void)
42 /* EC is trusted if not in RW. */
43 return !get_gpio(EC_IN_RW_GPIO);