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mb/google/poppy/atlas: Enable trackpad
[coreboot.git] / src / mainboard / google / poppy / variants / atlas / devicetree.cb
blob444454978456efdabe32435594b181c04d656b46
1 chip soc/intel/skylake
2
3 # Deep Sx states
4 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "0"
6 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
8 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
9
10 # GPE configuration
11 # Note that GPE events called out in ASL code rely on this
12 # route. i.e. If this route changes then the affected GPE
13 # offset bits also need to be changed.
14 register "gpe0_dw0" = "GPP_B"
15 register "gpe0_dw1" = "GPP_D"
16 register "gpe0_dw2" = "GPP_E"
17
18 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
19 register "gen1_dec" = "0x00fc0801"
20 register "gen2_dec" = "0x000c0201"
21 # EC memory map range is 0x900-0x9ff
22 register "gen3_dec" = "0x00fc0901"
23
24 # Enable DPTF
25 register "dptf_enable" = "1"
26
27 # Enable S0ix
28 register "s0ix_enable" = "1"
29
30 # FSP Configuration
31 register "ProbelessTrace" = "0"
32 register "EnableLan" = "0"
33 register "EnableSata" = "0"
34 register "SataSalpSupport" = "0"
35 register "SataMode" = "0"
36 register "SataPortsEnable[0]" = "0"
37 register "EnableAzalia" = "1"
38 register "DspEnable" = "1"
39 register "IoBufferOwnership" = "3"
40 register "EnableTraceHub" = "0"
41 register "SsicPortEnable" = "0"
42 register "SmbusEnable" = "1"
43 register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready
44 register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready
45 register "ScsEmmcEnabled" = "1"
46 register "ScsEmmcHs400Enabled" = "1"
47 register "ScsSdCardEnabled" = "0"
48 register "IshEnable" = "0" # FIXME: enable once ISH is ready
49 register "PttSwitch" = "0"
50 register "InternalGfx" = "1"
51 register "SkipExtGfxScan" = "1"
52 register "Device4Enable" = "1"
53 register "HeciEnabled" = "0"
54 register "FspSkipMpInit" = "1"
55 register "SaGv" = "3"
56 register "SerialIrqConfigSirqEnable" = "1"
57 register "PmConfigSlpS3MinAssert" = "2" # 50ms
58 register "PmConfigSlpS4MinAssert" = "1" # 1s
59 register "PmConfigSlpSusMinAssert" = "1" # 500ms
60 register "PmConfigSlpAMinAssert" = "3" # 2s
61 register "PmTimerDisabled" = "1"
62 register "VmxEnable" = "1"
63
64 register "speed_shift_enable" = "1"
65 register "dptf_enable" = "1"
66 register "tdp_pl2_override" = "15"
67 register "psys_pmax" = "45"
68 register "tcc_offset" = "10"
69 register "pch_trip_temp" = "75"
70 register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
71
72 register "pirqa_routing" = "PCH_IRQ11"
73 register "pirqb_routing" = "PCH_IRQ10"
74 register "pirqc_routing" = "PCH_IRQ11"
75 register "pirqd_routing" = "PCH_IRQ11"
76 register "pirqe_routing" = "PCH_IRQ11"
77 register "pirqf_routing" = "PCH_IRQ11"
78 register "pirqg_routing" = "PCH_IRQ11"
79 register "pirqh_routing" = "PCH_IRQ11"
80
81 # VR Settings Configuration for 4 Domains
82 #+----------------+-------+-------+-------+-------+
83 #| Domain/Setting | SA | IA | GTUS | GTS |
84 #+----------------+-------+-------+-------+-------+
85 #| Psi1Threshold | 20A | 20A | 20A | 20A |
86 #| Psi2Threshold | 2A | 2A | 2A | 2A |
87 #| Psi3Threshold | 1A | 1A | 1A | 1A |
88 #| Psi3Enable | 1 | 1 | 1 | 1 |
89 #| Psi4Enable | 1 | 1 | 1 | 1 |
90 #| ImonSlope | 0 | 0 | 0 | 0 |
91 #| ImonOffset | 0 | 0 | 0 | 0 |
92 #| IccMax | 4A | 24A | 24A | 24A |
93 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
94 #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 |
95 #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 |
96 #+----------------+-------+-------+-------+-------+
97 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
98 .vr_config_enable = 1,
99 .psi1threshold = VR_CFG_AMP(20),
100 .psi2threshold = VR_CFG_AMP(2),
101 .psi3threshold = VR_CFG_AMP(1),
102 .psi3enable = 1,
103 .psi4enable = 1,
104 .imon_slope = 0x0,
105 .imon_offset = 0x0,
106 .icc_max = VR_CFG_AMP(4),
107 .voltage_limit = 1520,
108 .ac_loadline = 1490,
109 .dc_loadline = 1420,
110 }"
111
112 register "domain_vr_config[VR_IA_CORE]" = "{
113 .vr_config_enable = 1,
114 .psi1threshold = VR_CFG_AMP(20),
115 .psi2threshold = VR_CFG_AMP(2),
116 .psi3threshold = VR_CFG_AMP(1),
117 .psi3enable = 1,
118 .psi4enable = 1,
119 .imon_slope = 0x0,
120 .imon_offset = 0x0,
121 .icc_max = VR_CFG_AMP(24),
122 .voltage_limit = 1520,
123 .ac_loadline = 500,
124 .dc_loadline = 486,
125 }"
126
127 register "domain_vr_config[VR_GT_UNSLICED]" = "{
128 .vr_config_enable = 1,
129 .psi1threshold = VR_CFG_AMP(20),
130 .psi2threshold = VR_CFG_AMP(2),
131 .psi3threshold = VR_CFG_AMP(1),
132 .psi3enable = 1,
133 .psi4enable = 1,
134 .imon_slope = 0x0,
135 .imon_offset = 0x0,
136 .icc_max = VR_CFG_AMP(24),
137 .voltage_limit = 1520,
138 .ac_loadline = 570,
139 .dc_loadline = 420,
140 }"
141
142 register "domain_vr_config[VR_GT_SLICED]" = "{
143 .vr_config_enable = 1,
144 .psi1threshold = VR_CFG_AMP(20),
145 .psi2threshold = VR_CFG_AMP(2),
146 .psi3threshold = VR_CFG_AMP(1),
147 .psi3enable = 1,
148 .psi4enable = 1,
149 .imon_slope = 0x0,
150 .imon_offset = 0x0,
151 .icc_max = VR_CFG_AMP(24),
152 .voltage_limit = 1520,
153 .ac_loadline = 457,
154 .dc_loadline = 430,
155 }"
156
157 # PCIe Root port 1 with SRCCLKREQ1#
158 register "PcieRpEnable[0]" = "1"
159 register "PcieRpClkReqSupport[0]" = "1"
160 register "PcieRpClkReqNumber[0]" = "1"
161 register "PcieRpClkSrcNumber[0]" = "1"
162 register "PcieRpAdvancedErrorReporting[0]" = "1"
163 register "PcieRpLtrEnable[0]" = "1"
164
165 # USB 2.0
166 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
167 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
168 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
169 register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
170 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty
171 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
172
173 # USB 3.0
174 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
175 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
176 register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
177 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
178
179 # Touchscreen
180 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
181 register "i2c[0]" = "{
182 .speed = I2C_SPEED_FAST,
183 .rise_time_ns = 98,
184 .fall_time_ns = 38,
185 }"
186
187 # Trackpad
188 register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
189 register "i2c[2]" = "{
190 .speed = I2C_SPEED_FAST,
191 .speed_config[0] = {
192 .speed = I2C_SPEED_FAST,
193 .scl_lcnt = 186,
194 .scl_hcnt = 93,
195 .sda_hold = 36,
196 },
197 }"
198
199 # Camera
200 register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
201 register "i2c[3]" = "{
202 .speed = I2C_SPEED_FAST,
203 .rise_time_ns = 98,
204 .fall_time_ns = 38,
205 }"
206
207 # Audio
208 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
209 register "i2c[4]" = "{
210 .speed = I2C_SPEED_FAST,
211 .speed_config[0] = {
212 .speed = I2C_SPEED_FAST,
213 .scl_lcnt = 176,
214 .scl_hcnt = 95,
215 .sda_hold = 36,
216 }
217 }"
218
219 # GSPI0 for cr50 TPM
220 register "gspi[0]" = "{
221 .speed_mhz = 1,
222 .early_init = 1,
223 }"
224
225 register "SerialIoDevMode" = "{
226 [PchSerialIoIndexI2C0] = PchSerialIoPci,
227 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
228 [PchSerialIoIndexI2C2] = PchSerialIoPci,
229 [PchSerialIoIndexI2C3] = PchSerialIoPci,
230 [PchSerialIoIndexI2C4] = PchSerialIoPci,
231 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
232 [PchSerialIoIndexSpi0] = PchSerialIoPci,
233 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
234 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
235 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
236 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
237 }"
238
239 device cpu_cluster 0 on
240 device lapic 0 on end
241 end
242 device domain 0 on
243 device pci 00.0 on end # Host Bridge
244 device pci 02.0 on end # Integrated Graphics Device
245 device pci 14.0 on end # USB xHCI
246 device pci 14.1 on end # USB xDCI (OTG)
247 device pci 14.2 on end # Thermal Subsystem
248 device pci 15.0 on end # I2C #0 - Touchscreen
249 device pci 15.1 off end # I2C #1
250 device pci 15.2 on
251 chip drivers/i2c/generic
252 register "hid" = ""ELAN0000""
253 register "desc" = ""ELAN Touchpad""
254 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)"
255 # TODO(caveh): fix wake source
256 #register "wake" = "GPE0_DWx_19" not possible?
257 register "probed" = "1" # may not be present
258 device i2c 0x15 on end
259 end
260 end # I2C #2 - Trackpad
261 device pci 15.3 on end # I2C #3 - Camera
262 device pci 16.0 on end # Management Engine Interface 1
263 device pci 16.1 off end # Management Engine Interface 2
264 device pci 16.2 off end # Management Engine IDE-R
265 device pci 16.3 off end # Management Engine KT Redirection
266 device pci 16.4 off end # Management Engine Interface 3
267 device pci 17.0 off end # SATA
268 device pci 19.0 on end # UART #2
269 device pci 19.1 off end # I2C #5
270 device pci 19.2 on
271 chip drivers/i2c/max98373
272 register "vmon_slot_no" = "4"
273 register "imon_slot_no" = "5"
274 register "uid" = "0"
275 register "desc" = ""RIGHT SPEAKER AMP""
276 register "name" = ""MAXR""
277 device i2c 31 on end
278 end
279 chip drivers/i2c/max98373
280 register "vmon_slot_no" = "6"
281 register "imon_slot_no" = "7"
282 register "uid" = "1"
283 register "desc" = ""LEFT SPEAKER AMP""
284 register "name" = ""MAXL""
285 device i2c 32 on end
286 end
287 chip drivers/i2c/da7219
288 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
289 register "btn_cfg" = "50"
290 register "mic_det_thr" = "500"
291 register "jack_ins_deb" = "20"
292 register "jack_det_rate" = ""32ms_64ms""
293 register "jack_rem_deb" = "1"
294 register "a_d_btn_thr" = "0xa"
295 register "d_b_btn_thr" = "0x16"
296 register "b_c_btn_thr" = "0x21"
297 register "c_mic_btn_thr" = "0x3e"
298 register "btn_avg" = "4"
299 register "adc_1bit_rpt" = "1"
300 register "micbias_lvl" = "2600"
301 register "mic_amp_in_sel" = ""diff""
302 device i2c 1a on end
303 end
304 end # I2C #4 - Audio
305 device pci 1c.0 on
306 chip drivers/intel/wifi
307 register "wake" = "GPE0_DW0_00"
308 device pci 00.0 on end
309 end
310 end # PCI Express Port 1
311 device pci 1c.1 off end # PCI Express Port 2
312 device pci 1c.2 off end # PCI Express Port 3
313 device pci 1c.3 off end # PCI Express Port 4
314 device pci 1c.4 off end # PCI Express Port 5
315 device pci 1c.5 off end # PCI Express Port 6
316 device pci 1c.6 off end # PCI Express Port 7
317 device pci 1c.7 off end # PCI Express Port 8
318 device pci 1d.0 off end # PCI Express Port 9
319 device pci 1d.1 off end # PCI Express Port 10
320 device pci 1d.2 off end # PCI Express Port 11
321 device pci 1d.3 off end # PCI Express Port 12
322 device pci 1e.0 on end # UART #0
323 device pci 1e.1 off end # UART #1
324 device pci 1e.2 on
325 chip drivers/spi/acpi
326 register "hid" = "ACPI_DT_NAMESPACE_HID"
327 register "compat_string" = ""google,cr50""
328 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
329 device spi 0 on end
330 end
331 end # GSPI #0
332 device pci 1e.3 off end # GSPI #1
333 device pci 1e.4 on end # eMMC
334 device pci 1e.5 off end # SDIO
335 device pci 1e.6 off end # SDCard
336 device pci 1f.0 on
337 chip ec/google/chromeec
338 device pnp 0c09.0 on end
339 end
340 end # LPC Interface
341 device pci 1f.1 on end # P2SB
342 device pci 1f.2 on end # Power Management Controller
343 device pci 1f.3 on end # Intel HDA
344 device pci 1f.4 on end # SMBus
345 device pci 1f.5 on end # PCH SPI
346 device pci 1f.6 off end # GbE
347 end
348 end
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