1 /* SPDX-License-Identifier: GPL-2.0-only */
5 #include <device/pci_ops.h>
6 #include <console/console.h>
7 #include <cpu/x86/cache.h>
8 #include <cpu/x86/smm.h>
9 #include <cpu/intel/em64t100_save_state.h>
10 #include <cpu/intel/em64t101_save_state.h>
12 #include <device/pci_def.h>
14 #include <intelblocks/fast_spi.h>
15 #include <intelblocks/pmclib.h>
16 #include <intelblocks/smihandler.h>
17 #include <intelblocks/tco.h>
18 #include <intelblocks/uart.h>
21 #include <soc/pci_devs.h>
24 #include <soc/iomap.h>
25 #include <soc/smbus.h>
26 #include <spi-generic.h>
31 __weak
const struct smm_save_state_ops
*get_smm_save_state_ops(void)
33 return &em64t101_smm_ops
;
36 /* Specific SOC SMI handler during ramstage finalize phase */
37 __weak
void smihandler_soc_at_finalize(void)
42 __weak
int smihandler_soc_disable_busmaster(pci_devfn_t dev
)
48 * Needs to implement the mechanism to know if an illegal attempt
49 * has been made to write to the BIOS area.
51 static void smihandler_soc_check_illegal_access(
54 if (!((tco_sts
& (1 << 8)) && CONFIG(SPI_FLASH_SMM
)
55 && fast_spi_wpd_status()))
59 * BWE is RW, so the SMI was caused by a
60 * write to BWE, not by a write to the BIOS
62 * This is the place where we notice someone
63 * is trying to tinker with the BIOS. We are
64 * trying to be nice and just ignore it. A more
65 * resolute answer would be to power down the
68 printk(BIOS_DEBUG
, "Switching back to RO\n");
72 /* Mainboard overrides. */
74 __weak
void mainboard_smi_gpi_handler(
75 const struct gpi_status
*sts
)
80 __weak
void mainboard_smi_espi_handler(void)
85 /* Common Functions */
87 static void *find_save_state(const struct smm_save_state_ops
*save_state_ops
,
92 uint32_t io_misc_info
;
95 /* Check all nodes looking for the one that issued the IO */
96 for (node
= 0; node
< CONFIG_MAX_CPUS
; node
++) {
97 state
= smm_get_save_state(node
);
99 io_misc_info
= save_state_ops
->get_io_misc_info(state
);
101 /* Check for Synchronous IO (bit0==1) */
102 if (!(io_misc_info
& (1 << 0)))
104 /* Make sure it was a write (bit4==0) */
105 if (io_misc_info
& (1 << 4))
107 /* Check for APMC IO port */
108 if (((io_misc_info
>> 16) & 0xff) != APM_CNT
)
110 /* Check AL against the requested command */
111 reg_al
= save_state_ops
->get_reg(state
, RAX
);
119 /* Inherited from cpu/x86/smm.h resulting in a different signature */
120 void southbridge_smi_set_eos(void)
125 static void busmaster_disable_on_bus(int bus
)
131 for (slot
= 0; slot
< 0x20; slot
++) {
132 for (func
= 0; func
< 8; func
++) {
135 pci_devfn_t dev
= PCI_DEV(bus
, slot
, func
);
137 if (!smihandler_soc_disable_busmaster(dev
))
139 val
= pci_read_config32(dev
, PCI_VENDOR_ID
);
141 if (val
== 0xffffffff || val
== 0x00000000 ||
142 val
== 0x0000ffff || val
== 0xffff0000)
145 /* Disable Bus Mastering for this one device */
146 reg16
= pci_read_config16(dev
, PCI_COMMAND
);
147 reg16
&= ~PCI_COMMAND_MASTER
;
148 pci_write_config16(dev
, PCI_COMMAND
, reg16
);
150 /* If it's not a bridge, move on. */
151 hdr
= pci_read_config8(dev
, PCI_HEADER_TYPE
);
153 if (hdr
!= PCI_HEADER_TYPE_BRIDGE
&&
154 hdr
!= PCI_HEADER_TYPE_CARDBUS
)
158 * If secondary bus is equal to current bus bypass
159 * the bridge because it's likely unconfigured and
160 * would cause infinite recursion.
162 int secbus
= pci_read_config8(dev
, PCI_SECONDARY_BUS
);
167 busmaster_disable_on_bus(secbus
);
172 void smihandler_southbridge_sleep(
173 const struct smm_save_state_ops
*save_state_ops
)
178 /* First, disable further SMIs */
179 pmc_disable_smi(SLP_SMI_EN
);
180 /* Figure out SLP_TYP */
181 reg32
= inl(ACPI_BASE_ADDRESS
+ PM1_CNT
);
182 printk(BIOS_SPEW
, "SMI#: SLP = 0x%08x\n", reg32
);
183 slp_typ
= acpi_sleep_from_pm1(reg32
);
185 /* Do any mainboard sleep handling */
186 mainboard_smi_sleep(slp_typ
);
188 /* Log S3, S4, and S5 entry */
189 if (slp_typ
>= ACPI_S3
)
190 elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER
, slp_typ
);
192 /* Clear pending GPE events */
193 pmc_clear_all_gpe_status();
195 /* Next, do the deed. */
199 printk(BIOS_DEBUG
, "SMI#: Entering S0 (On)\n");
202 printk(BIOS_DEBUG
, "SMI#: Entering S3 (Suspend-To-RAM)\n");
204 gnvs
->uior
= uart_is_controller_initialized();
206 /* Invalidate the cache before going to S3 */
210 printk(BIOS_DEBUG
, "SMI#: Entering S4 (Suspend-To-Disk)\n");
213 printk(BIOS_DEBUG
, "SMI#: Entering S5 (Soft Power off)\n");
215 /* Disable all GPE */
216 pmc_disable_all_gpe();
217 /* Set which state system will be after power reapplied */
218 pmc_set_power_failure_state(false);
219 /* also iterates over all bridges on bus 0 */
220 busmaster_disable_on_bus(0);
223 * Some platforms (e.g. Chromebooks) have observed race between
224 * SLP SMI and PWRBTN SMI because of the way these SMIs are
225 * triggered on power button press. Allow adding a delay before
226 * triggering sleep enable for S5, so that power button
227 * interrupt does not result into immediate wake.
229 mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
);
232 * Ensure any pending power button status bits are cleared as
233 * the system is entering S5 and doesn't want to be woken up
234 * right away from older power button events.
236 pmc_clear_pm1_status();
240 printk(BIOS_DEBUG
, "SMI#: ERROR: SLP_TYP reserved\n");
244 /* Tri-state specific GPIOS to avoid leakage during S3/S5 */
247 * Write back to the SLP register to cause the originally intended
248 * event again. We need to set BIT13 (SLP_EN) though to make the
251 pmc_enable_pm1_control(SLP_EN
);
253 /* Make sure to stop executing code here for S3/S4/S5 */
254 if (slp_typ
>= ACPI_S3
)
258 * In most sleep states, the code flow of this function ends at
259 * the line above. However, if we entered sleep state S1 and wake
260 * up again, we will continue to execute code in this function.
262 if (pmc_read_pm1_control() & SCI_EN
) {
263 /* The OS is not an ACPI OS, so we set the state to S0 */
264 pmc_disable_pm1_control(SLP_EN
| SLP_TYP
);
268 static void southbridge_smi_gsmi(
269 const struct smm_save_state_ops
*save_state_ops
)
275 io_smi
= find_save_state(save_state_ops
, APM_CNT_ELOG_GSMI
);
278 /* Command and return value in EAX */
279 sub_command
= (save_state_ops
->get_reg(io_smi
, RAX
) >> 8)
282 /* Parameter buffer in EBX */
283 reg_ebx
= save_state_ops
->get_reg(io_smi
, RBX
);
285 /* drivers/elog/gsmi.c */
286 ret
= gsmi_exec(sub_command
, ®_ebx
);
287 save_state_ops
->set_reg(io_smi
, RAX
, ret
);
290 static void southbridge_smi_store(
291 const struct smm_save_state_ops
*save_state_ops
)
297 io_smi
= find_save_state(save_state_ops
, APM_CNT_SMMSTORE
);
300 /* Command and return value in EAX */
301 sub_command
= (save_state_ops
->get_reg(io_smi
, RAX
) >> 8) & 0xff;
303 /* Parameter buffer in EBX */
304 reg_ebx
= save_state_ops
->get_reg(io_smi
, RBX
);
306 /* drivers/smmstore/smi.c */
307 ret
= smmstore_exec(sub_command
, (void *)reg_ebx
);
308 save_state_ops
->set_reg(io_smi
, RAX
, ret
);
311 static void finalize(void)
313 static int finalize_done
;
316 printk(BIOS_DEBUG
, "SMM already finalized.\n");
321 if (CONFIG(SPI_FLASH_SMM
))
322 /* Re-init SPI driver to handle locked BAR */
325 /* Specific SOC SMI handler during ramstage finalize phase */
326 smihandler_soc_at_finalize();
329 void smihandler_southbridge_apmc(
330 const struct smm_save_state_ops
*save_state_ops
)
334 static int smm_initialized
= 0;
336 /* Emulate B2 register as the FADT / Linux expects it */
340 case APM_CNT_CST_CONTROL
:
342 * Calling this function seems to cause
343 * some kind of race condition in Linux
344 * and causes a kernel oops
346 printk(BIOS_DEBUG
, "C-state control\n");
348 case APM_CNT_PST_CONTROL
:
350 * Calling this function seems to cause
351 * some kind of race condition in Linux
352 * and causes a kernel oops
354 printk(BIOS_DEBUG
, "P-state control\n");
356 case APM_CNT_ACPI_DISABLE
:
357 pmc_disable_pm1_control(SCI_EN
);
358 printk(BIOS_DEBUG
, "SMI#: ACPI disabled.\n");
360 case APM_CNT_ACPI_ENABLE
:
361 pmc_enable_pm1_control(SCI_EN
);
362 printk(BIOS_DEBUG
, "SMI#: ACPI enabled.\n");
364 case APM_CNT_GNVS_UPDATE
:
365 if (smm_initialized
) {
367 "SMI#: SMM structures already initialized!\n");
370 state
= find_save_state(save_state_ops
, reg8
);
372 /* EBX in the state save contains the GNVS pointer */
373 uint32_t reg_ebx
= save_state_ops
->get_reg(state
, RBX
);
374 gnvs
= (struct global_nvs
*)(uintptr_t)reg_ebx
;
375 if (smm_points_to_smram(gnvs
, sizeof(*gnvs
))) {
376 printk(BIOS_ERR
, "SMI#: ERROR: GNVS overlaps SMM\n");
380 printk(BIOS_DEBUG
, "SMI#: Setting GNVS to %p\n", gnvs
);
383 case APM_CNT_ELOG_GSMI
:
384 if (CONFIG(ELOG_GSMI
))
385 southbridge_smi_gsmi(save_state_ops
);
387 case APM_CNT_SMMSTORE
:
388 if (CONFIG(SMMSTORE
))
389 southbridge_smi_store(save_state_ops
);
391 case APM_CNT_FINALIZE
:
396 mainboard_smi_apmc(reg8
);
399 void smihandler_southbridge_pm1(
400 const struct smm_save_state_ops
*save_state_ops
)
402 uint16_t pm1_sts
= pmc_clear_pm1_status();
403 u16 pm1_en
= pmc_read_pm1_enable();
406 * While OSPM is not active, poweroff immediately
407 * on a power button event.
409 if ((pm1_sts
& PWRBTN_STS
) && (pm1_en
& PWRBTN_EN
)) {
410 /* power button pressed */
411 elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON
);
412 pmc_disable_pm1_control(-1UL);
413 pmc_enable_pm1_control(SLP_EN
| (SLP_TYP_S5
<< SLP_TYP_SHIFT
));
417 void smihandler_southbridge_gpe0(
418 const struct smm_save_state_ops
*save_state_ops
)
420 pmc_clear_all_gpe_status();
423 void smihandler_southbridge_tco(
424 const struct smm_save_state_ops
*save_state_ops
)
426 uint32_t tco_sts
= pmc_clear_tco_status();
432 smihandler_soc_check_illegal_access(tco_sts
);
434 if (tco_sts
& TCO_TIMEOUT
) { /* TIMEOUT */
435 /* Handle TCO timeout */
436 printk(BIOS_DEBUG
, "TCO Timeout.\n");
439 if (tco_sts
& (TCO_INTRD_DET
<< 16)) { /* INTRUDER# assertion */
441 * Handle intrusion event
442 * If we ever get here, probably the case has been opened.
444 printk(BIOS_CRIT
, "Case intrusion detected.\n");
448 void smihandler_southbridge_periodic(
449 const struct smm_save_state_ops
*save_state_ops
)
453 reg32
= pmc_get_smi_en();
455 /* Are periodic SMIs enabled? */
456 if ((reg32
& PERIODIC_EN
) == 0)
458 printk(BIOS_DEBUG
, "Periodic SMI.\n");
461 void smihandler_southbridge_gpi(
462 const struct smm_save_state_ops
*save_state_ops
)
464 struct gpi_status smi_sts
;
466 gpi_clear_get_smi_status(&smi_sts
);
467 mainboard_smi_gpi_handler(&smi_sts
);
469 /* Clear again after mainboard handler */
470 gpi_clear_get_smi_status(&smi_sts
);
473 void smihandler_southbridge_espi(
474 const struct smm_save_state_ops
*save_state_ops
)
476 mainboard_smi_espi_handler();
479 /* SMI handlers that should be serviced in SCI mode too. */
480 static uint32_t smihandler_soc_get_sci_mask(void)
483 SMI_HANDLER_SCI_EN(APM_STS_BIT
) |
484 SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT
);
489 void southbridge_smi_handler(void)
493 const struct smm_save_state_ops
*save_state_ops
;
496 * We need to clear the SMI status registers, or we won't see what's
497 * happening in the following calls.
499 smi_sts
= pmc_clear_smi_status();
502 * In SCI mode, execute only those SMI handlers that have
503 * declared themselves as available for service in that mode
504 * using smihandler_soc_get_sci_mask.
506 if (pmc_read_pm1_control() & SCI_EN
)
507 smi_sts
&= smihandler_soc_get_sci_mask();
512 save_state_ops
= get_smm_save_state_ops();
514 /* Call SMI sub handler for each of the status bits */
515 for (i
= 0; i
< ARRAY_SIZE(southbridge_smi
); i
++) {
516 if (!(smi_sts
& (1 << i
)))
519 if (southbridge_smi
[i
] != NULL
) {
520 southbridge_smi
[i
](save_state_ops
);
523 "SMI_STS[%d] occurred, but no "
524 "handler available.\n", i
);
529 static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state
)
531 em64t100_smm_state_save_area_t
*smm_state
= state
;
532 return smm_state
->io_misc_info
;
535 static uint64_t em64t100_smm_save_state_get_reg(void *state
, enum smm_reg reg
)
538 em64t100_smm_state_save_area_t
*smm_state
= state
;
542 value
= smm_state
->rax
;
545 value
= smm_state
->rbx
;
548 value
= smm_state
->rcx
;
551 value
= smm_state
->rdx
;
559 static void em64t100_smm_save_state_set_reg(void *state
, enum smm_reg reg
,
562 em64t100_smm_state_save_area_t
*smm_state
= state
;
565 smm_state
->rax
= val
;
568 smm_state
->rbx
= val
;
571 smm_state
->rcx
= val
;
574 smm_state
->rdx
= val
;
581 static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state
)
583 em64t101_smm_state_save_area_t
*smm_state
= state
;
584 return smm_state
->io_misc_info
;
587 static uint64_t em64t101_smm_save_state_get_reg(void *state
, enum smm_reg reg
)
590 em64t101_smm_state_save_area_t
*smm_state
= state
;
594 value
= smm_state
->rax
;
597 value
= smm_state
->rbx
;
600 value
= smm_state
->rcx
;
603 value
= smm_state
->rdx
;
611 static void em64t101_smm_save_state_set_reg(void *state
, enum smm_reg reg
,
614 em64t101_smm_state_save_area_t
*smm_state
= state
;
617 smm_state
->rax
= val
;
620 smm_state
->rbx
= val
;
623 smm_state
->rcx
= val
;
626 smm_state
->rdx
= val
;
633 const struct smm_save_state_ops em64t100_smm_ops
= {
634 .get_io_misc_info
= em64t100_smm_save_state_get_io_misc_info
,
635 .get_reg
= em64t100_smm_save_state_get_reg
,
636 .set_reg
= em64t100_smm_save_state_set_reg
,
639 const struct smm_save_state_ops em64t101_smm_ops
= {
640 .get_io_misc_info
= em64t101_smm_save_state_get_io_misc_info
,
641 .get_reg
= em64t101_smm_save_state_get_reg
,
642 .set_reg
= em64t101_smm_save_state_set_reg
,