src/soc/intel/broadwell/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_def.h>
   8 #include <soc/iobp.h>
   9 #include <soc/pch.h>
  10 #include <soc/pci_devs.h>
  11 #include <soc/ramstage.h>
  12 #include <soc/rcba.h>
  13 #include <soc/serialio.h>
  14 #include <soc/spi.h>
  15
  16 u8 pch_revision(void)
  17 {
  18         return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);
  19 }
  20
  21 u16 pch_type(void)
  22 {
  23         return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
  24 }
  25
  26 /* Return 1 if PCH type is WildcatPoint */
  27 int pch_is_wpt(void)
  28 {
  29         return ((pch_type() & 0xfff0) == 0x9cc0) ? 1 : 0;
  30 }
  31
  32 /* Return 1 if PCH type is WildcatPoint ULX */
  33 int pch_is_wpt_ulx(void)
  34 {
  35         u16 lpcid = pch_type();
  36
  37         switch (lpcid) {
  38         case PCH_WPT_BDW_Y_SAMPLE:
  39         case PCH_WPT_BDW_Y_PREMIUM:
  40         case PCH_WPT_BDW_Y_BASE:
  41                 return 1;
  42         }
  43
  44         return 0;
  45 }
  46
  47 u32 pch_read_soft_strap(int id)
  48 {
  49         u32 fdoc;
  50
  51         fdoc = SPIBAR32(SPIBAR_FDOC);
  52         fdoc &= ~0x00007ffc;
  53         SPIBAR32(SPIBAR_FDOC) = fdoc;
  54
  55         fdoc |= 0x00004000;
  56         fdoc |= id * 4;
  57         SPIBAR32(SPIBAR_FDOC) = fdoc;
  58
  59         return SPIBAR32(SPIBAR_FDOD);
  60 }
  61
  62 #ifndef __SIMPLE_DEVICE__
  63
  64 /* Put device in D3Hot Power State */
  65 static void pch_enable_d3hot(struct device *dev)
  66 {
  67         u32 reg32 = pci_read_config32(dev, PCH_PCS);
  68         reg32 |= PCH_PCS_PS_D3HOT;
  69         pci_write_config32(dev, PCH_PCS, reg32);
  70 }
  71
  72 /* RCBA function disable and posting read to flush the transaction */
  73 static void rcba_function_disable(u32 reg, u32 bit)
  74 {
  75         RCBA32_OR(reg, bit);
  76         RCBA32(reg);
  77 }
  78
  79 /* Set bit in Function Disable register to hide this device */
  80 void pch_disable_devfn(struct device *dev)
  81 {
  82         switch (dev->path.pci.devfn) {
  83         case PCH_DEVFN_ADSP: /* Audio DSP */
  84                 rcba_function_disable(FD, PCH_DISABLE_ADSPD);
  85                 break;
  86         case PCH_DEVFN_XHCI: /* XHCI */
  87                 rcba_function_disable(FD, PCH_DISABLE_XHCI);
  88                 break;
  89         case PCH_DEVFN_SDMA: /* DMA */
  90                 pch_enable_d3hot(dev);
  91                 pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
  92                 break;
  93         case PCH_DEVFN_I2C0: /* I2C0 */
  94                 pch_enable_d3hot(dev);
  95                 pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
  96                 break;
  97         case PCH_DEVFN_I2C1: /* I2C1 */
  98                 pch_enable_d3hot(dev);
  99                 pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 100                 break;
 101         case PCH_DEVFN_SPI0: /* SPI0 */
 102                 pch_enable_d3hot(dev);
 103                 pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 104                 break;
 105         case PCH_DEVFN_SPI1: /* SPI1 */
 106                 pch_enable_d3hot(dev);
 107                 pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 108                 break;
 109         case PCH_DEVFN_UART0: /* UART0 */
 110                 pch_enable_d3hot(dev);
 111                 pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 112                 break;
 113         case PCH_DEVFN_UART1: /* UART1 */
 114                 pch_enable_d3hot(dev);
 115                 pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 116                 break;
 117         case PCH_DEVFN_ME: /* MEI #1 */
 118                 rcba_function_disable(FD2, PCH_DISABLE_MEI1);
 119                 break;
 120         case PCH_DEVFN_ME_2: /* MEI #2 */
 121                 rcba_function_disable(FD2, PCH_DISABLE_MEI2);
 122                 break;
 123         case PCH_DEVFN_ME_IDER: /* IDE-R */
 124                 rcba_function_disable(FD2, PCH_DISABLE_IDER);
 125                 break;
 126         case PCH_DEVFN_ME_KT: /* KT */
 127                 rcba_function_disable(FD2, PCH_DISABLE_KT);
 128                 break;
 129         case PCH_DEVFN_SDIO: /* SDIO */
 130                 pch_enable_d3hot(dev);
 131                 pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
 132                 break;
 133         case PCH_DEVFN_GBE: /* Gigabit Ethernet */
 134                 rcba_function_disable(BUC, PCH_DISABLE_GBE);
 135                 break;
 136         case PCH_DEVFN_HDA: /* HD Audio Controller */
 137                 rcba_function_disable(FD, PCH_DISABLE_HD_AUDIO);
 138                 break;
 139         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */
 140         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */
 141         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */
 142         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */
 143         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */
 144         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */
 145         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */
 146         case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */
 147                 rcba_function_disable(FD,
 148                         PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
 149                 break;
 150         case PCH_DEVFN_EHCI: /* EHCI #1 */
 151                 rcba_function_disable(FD, PCH_DISABLE_EHCI1);
 152                 break;
 153         case PCH_DEVFN_LPC: /* LPC */
 154                 rcba_function_disable(FD, PCH_DISABLE_LPC);
 155                 break;
 156         case PCH_DEVFN_SATA: /* SATA #1 */
 157                 rcba_function_disable(FD, PCH_DISABLE_SATA1);
 158                 break;
 159         case PCH_DEVFN_SMBUS: /* SMBUS */
 160                 rcba_function_disable(FD, PCH_DISABLE_SMBUS);
 161                 break;
 162         case PCH_DEVFN_SATA2: /* SATA #2 */
 163                 rcba_function_disable(FD, PCH_DISABLE_SATA2);
 164                 break;
 165         case PCH_DEVFN_THERMAL: /* Thermal Subsystem */
 166                 rcba_function_disable(FD, PCH_DISABLE_THERMAL);
 167                 break;
 168         }
 169 }
 170
 171 void broadwell_pch_enable_dev(struct device *dev)
 172 {
 173         u16 reg16;
 174
 175         /* These devices need special enable/disable handling */
 176         switch (PCI_SLOT(dev->path.pci.devfn)) {
 177         case PCH_DEV_SLOT_PCIE:
 178         case PCH_DEV_SLOT_EHCI:
 179         case PCH_DEV_SLOT_HDA:
 180                 return;
 181         }
 182
 183         if (!dev->enabled) {
 184                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 185
 186                 /* Ensure memory, io, and bus master are all disabled */
 187                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 188                 reg16 &= ~(PCI_COMMAND_MASTER |
 189                            PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 190                 pci_write_config16(dev, PCI_COMMAND, reg16);
 191
 192                 /* Disable this device if possible */
 193                 pch_disable_devfn(dev);
 194         } else {
 195                 /* Enable SERR */
 196                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 197         }
 198 }
 199
 200 #endif