src/soc/intel/braswell/romstage/romstage.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cbmem.h>
   4 #include <stdint.h>
   5 #include <arch/io.h>
   6 #include <device/mmio.h>
   7 #include <console/console.h>
   8 #include <soc/iomap.h>
   9 #include <soc/iosf.h>
  10 #include <soc/romstage.h>
  11
  12 #include "../chip.h"
  13
  14 static struct chipset_power_state power_state;
  15
  16 static void migrate_power_state(int is_recovery)
  17 {
  18         struct chipset_power_state *ps_cbmem;
  19
  20         ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
  21
  22         if (ps_cbmem == NULL) {
  23                 printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
  24                 return;
  25         }
  26         memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem));
  27 }
  28 ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state);
  29
  30 struct chipset_power_state *fill_power_state(void)
  31 {
  32         power_state.pm1_sts  = inw(ACPI_BASE_ADDRESS + PM1_STS);
  33         power_state.pm1_en   = inw(ACPI_BASE_ADDRESS + PM1_EN);
  34         power_state.pm1_cnt  = inl(ACPI_BASE_ADDRESS + PM1_CNT);
  35         power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
  36         power_state.gpe0_en  = inl(ACPI_BASE_ADDRESS + GPE0_EN);
  37         power_state.tco_sts  = inl(ACPI_BASE_ADDRESS + TCO_STS);
  38
  39         power_state.prsts      = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
  40         power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
  41         power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2));
  42
  43         power_state.prev_sleep_state = chipset_prev_sleep_state(&power_state);
  44
  45         printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
  46                 power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt);
  47
  48         printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n",
  49                 power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts);
  50
  51         printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n",
  52                 power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2);
  53
  54         printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state);
  55         return &power_state;
  56 }
  57
  58 /* Return 0, 3, or 5 to indicate the previous sleep state. */
  59 int chipset_prev_sleep_state(struct chipset_power_state *ps)
  60 {
  61         /* Default to S0. */
  62         int prev_sleep_state = ACPI_S0;
  63
  64         if (ps->pm1_sts & WAK_STS) {
  65                 switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
  66                 case ACPI_S3:
  67                         if (CONFIG(HAVE_ACPI_RESUME))
  68                                 prev_sleep_state = ACPI_S3;
  69                         break;
  70                 case ACPI_S5:
  71                         prev_sleep_state = ACPI_S5;
  72                         break;
  73                 }
  74
  75                 /* Clear SLP_TYP. */
  76                 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
  77         }
  78
  79         if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
  80                 prev_sleep_state = ACPI_S5;
  81
  82         return prev_sleep_state;
  83 }
  84
  85 /* SOC initialization after RAM is enabled */
  86 void soc_after_ram_init(struct romstage_params *params)
  87 {
  88         u32 value;
  89
  90         /* Make sure that E0000 and F0000 are RAM */
  91         printk(BIOS_DEBUG, "Disable ROM shadow below 1MB.\n");
  92         value = iosf_bunit_read(BUNIT_BMISC);
  93         value |= 3;
  94         iosf_bunit_write(BUNIT_BMISC, value);
  95 }
  96
  97 /* Initialize the UPD parameters for MemoryInit */
  98 void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd)
  99 {
 100         const struct device *dev;
 101         const struct soc_intel_braswell_config *config;
 102
 103         /* Set the parameters for MemoryInit */
 104         dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
 105
 106         if (!dev) {
 107                 printk(BIOS_ERR,
 108                         "Error! Device (PCI:0:%02x.%01x) not found, soc_memory_init_params!\n",
 109                         LPC_DEV, LPC_FUNC);
 110                 return;
 111         }
 112
 113         config = config_of(dev);
 114         printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
 115
 116         upd->PcdMrcInitTsegSize   = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0;
 117         upd->PcdMrcInitMmioSize   = config->PcdMrcInitMmioSize;
 118         upd->PcdMrcInitSpdAddr1   = config->PcdMrcInitSpdAddr1;
 119         upd->PcdMrcInitSpdAddr2   = config->PcdMrcInitSpdAddr2;
 120         upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
 121         upd->PcdApertureSize      = config->PcdApertureSize;
 122         upd->PcdGttSize           = config->PcdGttSize;
 123         upd->PcdLegacySegDecode   = config->PcdLegacySegDecode;
 124         upd->PcdDvfsEnable        = config->PcdDvfsEnable;
 125         upd->PcdCaMirrorEn        = config->PcdCaMirrorEn;
 126 }
 127
 128 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 129         MEMORY_INIT_UPD *new)
 130 {
 131         /* Display the parameters for MemoryInit */
 132         printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
 133         fsp_display_upd_value("PcdMrcInitTsegSize", 2,
 134                           old->PcdMrcInitTsegSize,
 135                           new->PcdMrcInitTsegSize);
 136         fsp_display_upd_value("PcdMrcInitMmioSize", 2,
 137                           old->PcdMrcInitMmioSize,
 138                           new->PcdMrcInitMmioSize);
 139         fsp_display_upd_value("PcdMrcInitSpdAddr1", 1,
 140                           old->PcdMrcInitSpdAddr1,
 141                           new->PcdMrcInitSpdAddr1);
 142         fsp_display_upd_value("PcdMrcInitSpdAddr2", 1,
 143                           old->PcdMrcInitSpdAddr2,
 144                           new->PcdMrcInitSpdAddr2);
 145         fsp_display_upd_value("PcdMemChannel0Config", 1,
 146                           old->PcdMemChannel0Config,
 147                           new->PcdMemChannel0Config);
 148         fsp_display_upd_value("PcdMemChannel1Config", 1,
 149                           old->PcdMemChannel1Config,
 150                           new->PcdMemChannel1Config);
 151         fsp_display_upd_value("PcdMemorySpdPtr", 4,
 152                           old->PcdMemorySpdPtr,
 153                           new->PcdMemorySpdPtr);
 154         fsp_display_upd_value("PcdIgdDvmt50PreAlloc", 1,
 155                           old->PcdIgdDvmt50PreAlloc,
 156                           new->PcdIgdDvmt50PreAlloc);
 157         fsp_display_upd_value("PcdApertureSize", 1,
 158                           old->PcdApertureSize,
 159                           new->PcdApertureSize);
 160         fsp_display_upd_value("PcdGttSize", 1,
 161                           old->PcdGttSize,
 162                           new->PcdGttSize);
 163         fsp_display_upd_value("PcdLegacySegDecode", 1,
 164                           old->PcdLegacySegDecode,
 165                           new->PcdLegacySegDecode);
 166         fsp_display_upd_value("PcdDvfsEnable", 1,
 167                           old->PcdDvfsEnable,
 168                           new->PcdDvfsEnable);
 169 }