src/soc/intel/braswell/lpe.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <acpi/acpi_gnvs.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <reg_script.h>
  11
  12 #include <soc/iomap.h>
  13 #include <soc/iosf.h>
  14 #include <soc/lpc.h>
  15 #include <soc/nvs.h>
  16 #include <soc/pattrs.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/pm.h>
  19 #include <soc/ramstage.h>
  20 #include "chip.h"
  21
  22 /*
  23  * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
  24  * address. Just take 1MiB @ 512MiB.
  25  */
  26 #define FIRMWARE_PHYS_BASE (512 << 20)
  27 #define FIRMWARE_PHYS_LENGTH (2 << 20)
  28 #define FIRMWARE_PCI_REG_BASE 0xa8
  29 #define FIRMWARE_PCI_REG_LENGTH 0xac
  30 #define FIRMWARE_REG_BASE_C0 0x144000
  31 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
  32
  33 static void assign_device_nvs(struct device *dev, u32 *field,
  34                               unsigned int index)
  35 {
  36         struct resource *res;
  37
  38         res = find_resource(dev, index);
  39         if (res)
  40                 *field = res->base;
  41 }
  42
  43 static void lpe_enable_acpi_mode(struct device *dev)
  44 {
  45         static const struct reg_script ops[] = {
  46                 /* Disable PCI interrupt, enable Memory and Bus Master */
  47                 REG_PCI_OR16(PCI_COMMAND,
  48                              PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
  49
  50                 /* Enable ACPI mode */
  51                 REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
  52                             LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN),
  53
  54                 REG_SCRIPT_END
  55         };
  56         struct global_nvs *gnvs;
  57
  58         /* Find ACPI NVS to update BARs */
  59         gnvs = acpi_get_gnvs();
  60         if (!gnvs)
  61                 return;
  62
  63         /* Save BAR0, BAR1, and firmware base  to ACPI NVS */
  64         assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
  65         assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2);
  66         assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
  67
  68         /* Device is enabled in ACPI mode */
  69         gnvs->dev.lpe_en = 1;
  70
  71         /* Put device in ACPI mode */
  72         reg_script_run_on_dev(dev, ops);
  73 }
  74
  75 static void setup_codec_clock(struct device *dev)
  76 {
  77         uint32_t reg;
  78         u32 *clk_reg;
  79         struct soc_intel_braswell_config *config;
  80         const char *freq_str;
  81
  82         config = config_of(dev);
  83         switch (config->lpe_codec_clk_src) {
  84         case LPE_CLK_SRC_XTAL:
  85                 /* XTAL driven bit2=0 */
  86                 freq_str = "19.2MHz External Crystal";
  87                 reg = CLK_SRC_XTAL;
  88                 break;
  89
  90         case LPE_CLK_SRC_PLL:
  91                 /* PLL driven bit2=1 */
  92                 freq_str = "19.2MHz PLL";
  93                 reg = CLK_SRC_PLL;
  94                 break;
  95
  96         default:
  97                 reg = CLK_SRC_XTAL;
  98                 printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n");
  99                 return;
 100         }
 101
 102         /* Default to always running. */
 103         reg |= CLK_CTL_ON;
 104
 105         printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
 106
 107         clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
 108
 109         write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
 110 }
 111
 112 static void lpe_stash_firmware_info(struct device *dev)
 113 {
 114         struct resource *res;
 115         struct resource *mmio;
 116
 117         res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
 118         if (res == NULL) {
 119                 printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
 120                 return;
 121         }
 122         printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
 123
 124         /* Continue using old way of informing firmware address / size. */
 125         pci_write_config32(dev, FIRMWARE_PCI_REG_BASE,   res->base);
 126         pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
 127
 128         /* Also put the address in MMIO space like on C0 BTM */
 129         mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
 130         write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),   res->base);
 131         write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size);
 132 }
 133
 134 static void lpe_init(struct device *dev)
 135 {
 136         struct soc_intel_braswell_config *config = config_of(dev);
 137
 138         lpe_stash_firmware_info(dev);
 139         setup_codec_clock(dev);
 140
 141         if (config->lpe_acpi_mode)
 142                 lpe_enable_acpi_mode(dev);
 143 }
 144
 145 static void lpe_read_resources(struct device *dev)
 146 {
 147         struct resource *res;
 148         pci_dev_read_resources(dev);
 149
 150         /*
 151          * Allocate the BAR1 resource at index 2 to fulfill the Windows driver
 152          * interface requirements even though the PCI device has only one BAR
 153          */
 154         res = new_resource(dev, PCI_BASE_ADDRESS_2);
 155         res->base = 0;
 156         res->size = 0x1000;
 157         res->limit = 0xffffffff;
 158         res->gran = 12;
 159         res->align = 12;
 160         res->flags = IORESOURCE_MEM;
 161
 162         reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10,
 163                               FIRMWARE_PHYS_LENGTH >> 10);
 164 }
 165
 166 static void lpe_set_resources(struct device *dev)
 167 {
 168         struct resource *res;
 169
 170         res = find_resource(dev, PCI_BASE_ADDRESS_2);
 171         if (res != NULL)
 172                 res->flags |= IORESOURCE_STORED;
 173
 174         pci_dev_set_resources(dev);
 175 }
 176
 177 static const struct device_operations device_ops = {
 178         .read_resources         = lpe_read_resources,
 179         .set_resources          = lpe_set_resources,
 180         .enable_resources       = pci_dev_enable_resources,
 181         .init                   = lpe_init,
 182         .ops_pci                = &soc_pci_ops,
 183 };
 184
 185 static const struct pci_driver southcluster __pci_driver = {
 186         .ops            = &device_ops,
 187         .vendor         = PCI_VENDOR_ID_INTEL,
 188         .device         = LPE_DEVID,
 189 };