src/mainboard/amd/persimmon/mptable.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/smp/mpspec.h>
   4 #include <stdint.h>
   5 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
   6 #include <southbridge/amd/common/amd_pci_util.h>
   7 #include <drivers/generic/ioapic/chip.h>
   8 #include <arch/ioapic.h>
   9
  10 static void *smp_write_config_table(void *v)
  11 {
  12         struct mp_config_table *mc;
  13         int bus_isa;
  14
  15         /*
  16          * By the time this function gets called, the IOAPIC registers
  17          * have been written so they can be read to get the correct
  18          * APIC ID and Version
  19          */
  20         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  21         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  22
  23         /* Initialize the MP_Table */
  24         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  25
  26         mptable_init(mc, LOCAL_APIC_ADDR);
  27
  28         /*
  29          * Type 0: Processor Entries:
  30          * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
  31          * CPU Signature (Stepping, Model, Family),
  32          * Feature Flags
  33          */
  34         smp_write_processors(mc);
  35
  36         /*
  37          * Type 1: Bus Entries:
  38          * Bus ID, Bus Type
  39          */
  40         mptable_write_buses(mc, NULL, &bus_isa);
  41
  42         /*
  43          * Type 2: I/O APICs:
  44          * APIC ID, Version, APIC Flags:EN, Address
  45          */
  46         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  47
  48         /*
  49          * Type 3: I/O Interrupt Table Entries:
  50          * Int Type, Int Polarity, Int Level, Source Bus ID,
  51          * Source Bus IRQ, Dest APIC ID, Dest PIN#
  52          */
  53         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
  54
  55         /* PCI interrupts are level triggered, and are
  56          * associated with a specific bus/device/function tuple.
  57          */
  58 #define PCI_INT(bus, dev, fn, pin) \
  59                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
  60
  61         /* APU Internal Graphic Device */
  62         PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
  63         PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
  64
  65         /* SMBUS / ACPI */
  66         PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
  67
  68         /* Southbridge HD Audio */
  69         PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
  70
  71         /* LPC */
  72         PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
  73
  74         /* USB */
  75         PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
  76         PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
  77         PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
  78         PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
  79         PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
  80
  81          /* IDE */
  82         PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
  83
  84         /* SATA */
  85         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
  86
  87         /* on board NIC & Slot PCIE */
  88         PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
  89         PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
  90
  91         /* PCI slots */
  92         struct device *dev = pcidev_on_root(0x14, 4);
  93         if (dev && dev->enabled) {
  94                 u8 bus_pci = dev->link_list->secondary;
  95                 /* PCI_SLOT 0 */
  96                 PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);      /* INTA -> INTE */
  97                 PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);      /* INTB -> INTF */
  98                 PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);      /* INTC -> INTG */
  99                 PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);      /* INTD -> INTH */
 100         }
 101
 102         /* PCIe PortA */
 103         PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
 104         /* PCIe PortB */
 105         PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
 106         /* PCIe PortC */
 107         PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
 108         /* PCIe PortD */
 109         PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
 110
 111         /*Local Ints:    Type   Polarity        Trigger  Bus ID  IRQ    APIC ID PIN# */
 112 #define IO_LOCAL_INT(type, intr, apicid, pin) \
 113                 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 114
 115         IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 116         IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 117         /* There is no extension information... */
 118
 119         /* Compute the checksums */
 120         return mptable_finalize(mc);
 121 }
 122
 123 unsigned long write_smp_table(unsigned long addr)
 124 {
 125         void *v;
 126         v = smp_write_floating_table(addr, 0);  /* ADDR, Enable Virtual Wire */
 127         return (unsigned long)smp_write_config_table(v);
 128 }