src/mainboard/amd/parmer/mptable.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/smp/mpspec.h>
   4 #include <arch/ioapic.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7 #include <southbridge/amd/common/amd_pci_util.h>
   8 #include <southbridge/amd/agesa/hudson/hudson.h>
   9
  10 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
  11 {
  12         mc->mpc_length += length;
  13         mc->mpc_entry_count++;
  14 }
  15
  16 static void my_smp_write_bus(struct mp_config_table *mc,
  17                              unsigned char id, const char *bustype)
  18 {
  19         struct mpc_config_bus *mpc;
  20         mpc = smp_next_mpc_entry(mc);
  21         memset(mpc, '\0', sizeof(*mpc));
  22         mpc->mpc_type = MP_BUS;
  23         mpc->mpc_busid = id;
  24         memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
  25         smp_add_mpc_entry(mc, sizeof(*mpc));
  26 }
  27
  28 static void *smp_write_config_table(void *v)
  29 {
  30         struct mp_config_table *mc;
  31         int bus_isa;
  32
  33         /*
  34          * By the time this function gets called, the IOAPIC registers
  35          * have been written so they can be read to get the correct
  36          * APIC ID and Version
  37          */
  38         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  39         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  40
  41         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  42
  43         mptable_init(mc, LOCAL_APIC_ADDR);
  44         memcpy(mc->mpc_oem, "AMD     ", 8);
  45
  46         smp_write_processors(mc);
  47
  48         //mptable_write_buses(mc, NULL, &bus_isa);
  49         my_smp_write_bus(mc, 0, "PCI   ");
  50         my_smp_write_bus(mc, 1, "PCI   ");
  51         bus_isa = 0x02;
  52         my_smp_write_bus(mc, bus_isa, "ISA   ");
  53
  54         /* I/O APICs:   APIC ID Version State   Address */
  55         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  56
  57         /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
  58 #define IO_LOCAL_INT(type, intr, apicid, pin)                           \
  59         smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
  60         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
  61
  62         /* PCI interrupts are level triggered, and are
  63          * associated with a specific bus/device/function tuple.
  64          */
  65 #define PCI_INT(bus, dev, int_sign, pin)                                \
  66         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
  67
  68         /* Internal VGA */
  69         PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
  70         PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
  71
  72         /* SMBUS */
  73         PCI_INT(0x0, 0x14, 0x0, 0x10);
  74
  75         /* HD Audio */
  76         PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
  77
  78         /* USB */
  79         PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
  80         PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
  81         PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
  82         PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
  83         PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
  84         PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
  85         PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
  86
  87         /* sata */
  88         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
  89         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
  90
  91         /* on board NIC & Slot PCIE.  */
  92
  93         /* PCI slots */
  94         struct device *dev = pcidev_on_root(0x14, 4);
  95         if (dev && dev->enabled) {
  96                 u8 bus_pci = dev->link_list->secondary;
  97                 /* PCI_SLOT 0. */
  98                 PCI_INT(bus_pci, 0x5, 0x0, 0x14);
  99                 PCI_INT(bus_pci, 0x5, 0x1, 0x15);
 100                 PCI_INT(bus_pci, 0x5, 0x2, 0x16);
 101                 PCI_INT(bus_pci, 0x5, 0x3, 0x17);
 102
 103                 /* PCI_SLOT 1. */
 104                 PCI_INT(bus_pci, 0x6, 0x0, 0x15);
 105                 PCI_INT(bus_pci, 0x6, 0x1, 0x16);
 106                 PCI_INT(bus_pci, 0x6, 0x2, 0x17);
 107                 PCI_INT(bus_pci, 0x6, 0x3, 0x14);
 108
 109                 /* PCI_SLOT 2. */
 110                 PCI_INT(bus_pci, 0x7, 0x0, 0x16);
 111                 PCI_INT(bus_pci, 0x7, 0x1, 0x17);
 112                 PCI_INT(bus_pci, 0x7, 0x2, 0x14);
 113                 PCI_INT(bus_pci, 0x7, 0x3, 0x15);
 114         }
 115
 116         /* PCIe Lan*/
 117         PCI_INT(0x0, 0x06, 0x0, 0x13);
 118
 119         /* FCH PCIe PortA */
 120         PCI_INT(0x0, 0x15, 0x0, 0x10);
 121         /* FCH PCIe PortB */
 122         PCI_INT(0x0, 0x15, 0x1, 0x11);
 123         /* FCH PCIe PortC */
 124         PCI_INT(0x0, 0x15, 0x2, 0x12);
 125         /* FCH PCIe PortD */
 126         PCI_INT(0x0, 0x15, 0x3, 0x13);
 127
 128         /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 129         IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
 130         IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
 131         /* There is no extension information... */
 132
 133         /* Compute the checksums */
 134         return mptable_finalize(mc);
 135 }
 136
 137 unsigned long write_smp_table(unsigned long addr)
 138 {
 139         void *v;
 140         v = smp_write_floating_table(addr, 0);
 141         return (unsigned long)smp_write_config_table(v);
 142 }