src/mainboard/amd/inagua/mptable.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/smp/mpspec.h>
   4 #include <arch/ioapic.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
   8 #include <southbridge/amd/common/amd_pci_util.h>
   9
  10 static void *smp_write_config_table(void *v)
  11 {
  12         struct mp_config_table *mc;
  13         int bus_isa;
  14
  15         /*
  16          * By the time this function gets called, the IOAPIC registers
  17          * have been written so they can be read to get the correct
  18          * APIC ID and Version
  19          */
  20         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  21         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  22
  23         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  24
  25         mptable_init(mc, LOCAL_APIC_ADDR);
  26         memcpy(mc->mpc_oem, "AMD     ", 8);
  27
  28         smp_write_processors(mc);
  29
  30         mptable_write_buses(mc, NULL, &bus_isa);
  31
  32         /* I/O APICs:   APIC ID Version State   Address */
  33         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  34
  35         /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
  36 #define IO_LOCAL_INT(type, intr, apicid, pin) \
  37         smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
  38
  39         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
  40
  41         /* PCI interrupts are level triggered, and are
  42          * associated with a specific bus/device/function tuple.
  43          */
  44 #define PCI_INT(bus, dev, fn, pin) \
  45         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
  46
  47         /* APU Internal Graphic Device*/
  48         PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
  49         PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
  50
  51         //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
  52         PCI_INT(0x0, 0x14, 0x0, 0x10);
  53         /* Southbridge HD Audio: */
  54         PCI_INT(0x0, 0x14, 0x2, 0x12);
  55
  56         PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
  57         PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
  58         PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
  59         PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
  60         PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
  61         PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
  62
  63         /* sata */
  64         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
  65
  66         /* on board NIC & Slot PCIE.  */
  67
  68         /* PCI slots */
  69         struct device *dev = pcidev_on_root(0x14, 4);
  70         if (dev && dev->enabled) {
  71                 u8 bus_pci = dev->link_list->secondary;
  72                 /* PCI_SLOT 0. */
  73                 PCI_INT(bus_pci, 0x5, 0x0, 0x14);
  74                 PCI_INT(bus_pci, 0x5, 0x1, 0x15);
  75                 PCI_INT(bus_pci, 0x5, 0x2, 0x16);
  76                 PCI_INT(bus_pci, 0x5, 0x3, 0x17);
  77
  78                 /* PCI_SLOT 1. */
  79                 PCI_INT(bus_pci, 0x6, 0x0, 0x15);
  80                 PCI_INT(bus_pci, 0x6, 0x1, 0x16);
  81                 PCI_INT(bus_pci, 0x6, 0x2, 0x17);
  82                 PCI_INT(bus_pci, 0x6, 0x3, 0x14);
  83
  84                 /* PCI_SLOT 2. */
  85                 PCI_INT(bus_pci, 0x7, 0x0, 0x16);
  86                 PCI_INT(bus_pci, 0x7, 0x1, 0x17);
  87                 PCI_INT(bus_pci, 0x7, 0x2, 0x14);
  88                 PCI_INT(bus_pci, 0x7, 0x3, 0x15);
  89         }
  90
  91         /* PCIe PortA */
  92         PCI_INT(0x0, 0x15, 0x0, 0x10);
  93         /* PCIe PortB */
  94         PCI_INT(0x0, 0x15, 0x1, 0x11);
  95         /* PCIe PortC */
  96         PCI_INT(0x0, 0x15, 0x2, 0x12);
  97         /* PCIe PortD */
  98         PCI_INT(0x0, 0x15, 0x3, 0x13);
  99
 100         /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 101         IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 102         IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 103         /* There is no extension information... */
 104
 105         /* Compute the checksums */
 106         return mptable_finalize(mc);
 107 }
 108
 109 unsigned long write_smp_table(unsigned long addr)
 110 {
 111         void *v;
 112         v = smp_write_floating_table(addr, 0);
 113         return (unsigned long)smp_write_config_table(v);
 114 }