1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/smp/mpspec.h>
4 #include <arch/ioapic.h>
7 #include <soc/southbridge.h>
8 #include <amdblocks/amd_pci_util.h>
10 static void smp_add_mpc_entry(struct mp_config_table
*mc
, unsigned int length
)
12 mc
->mpc_length
+= length
;
13 mc
->mpc_entry_count
++;
16 static void my_smp_write_bus(struct mp_config_table
*mc
,
17 unsigned char id
, const char *bustype
)
19 struct mpc_config_bus
*mpc
;
20 mpc
= smp_next_mpc_entry(mc
);
21 memset(mpc
, '\0', sizeof(*mpc
));
22 mpc
->mpc_type
= MP_BUS
;
24 memcpy(mpc
->mpc_bustype
, bustype
, sizeof(mpc
->mpc_bustype
));
25 smp_add_mpc_entry(mc
, sizeof(*mpc
));
28 static void *smp_write_config_table(void *v
)
30 struct mp_config_table
*mc
;
34 * By the time this function gets called, the IOAPIC registers
35 * have been written so they can be read to get the correct
38 u8 ioapic_id
= (io_apic_read(VIO_APIC_VADDR
, 0x00) >> 24);
39 u8 ioapic_ver
= (io_apic_read(VIO_APIC_VADDR
, 0x01) & 0xFF);
41 mc
= (void *)(((char *)v
) + SMP_FLOATING_TABLE_LEN
);
43 mptable_init(mc
, LOCAL_APIC_ADDR
);
44 memcpy(mc
->mpc_oem
, "AMD ", 8);
46 smp_write_processors(mc
);
48 //mptable_write_buses(mc, NULL, &bus_isa);
49 my_smp_write_bus(mc
, 0, "PCI ");
50 my_smp_write_bus(mc
, 1, "PCI ");
52 my_smp_write_bus(mc
, bus_isa
, "ISA ");
54 /* I/O APICs: APIC ID Version State Address */
55 smp_write_ioapic(mc
, ioapic_id
, ioapic_ver
, VIO_APIC_VADDR
);
57 smp_write_ioapic(mc
, ioapic_id
+1, 0x21, (void *)0xFEC20000);
59 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
60 #define IO_LOCAL_INT(type, intr, apicid, pin) \
61 smp_write_lintsrc(mc, (type), \
62 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
63 (intr), (apicid), (pin))
64 mptable_add_isa_interrupts(mc
, bus_isa
, ioapic_id
, 0);
66 /* PCI interrupts are level triggered, and are
67 * associated with a specific bus/device/function tuple.
69 #define PCI_INT(bus, dev, int_sign, pin) \
70 smp_write_intsrc(mc, mp_INT, \
71 MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
72 (((dev)<<2)|(int_sign)), ioapic_id, (pin))
75 PCI_INT(0x0, 0x01, 0x0, intr_data_ptr
[0x02]);
76 PCI_INT(0x0, 0x01, 0x1, intr_data_ptr
[0x03]);
79 PCI_INT(0x0, 0x14, 0x0, 0x10);
82 PCI_INT(0x0, 0x14, 0x0, intr_data_ptr
[0x13]);
85 PCI_INT(0x0, 0x12, 0x0, intr_data_ptr
[0x30]);
86 PCI_INT(0x0, 0x12, 0x1, intr_data_ptr
[0x31]);
87 PCI_INT(0x0, 0x13, 0x0, intr_data_ptr
[0x32]);
88 PCI_INT(0x0, 0x13, 0x1, intr_data_ptr
[0x33]);
89 PCI_INT(0x0, 0x16, 0x0, intr_data_ptr
[0x34]);
90 PCI_INT(0x0, 0x16, 0x1, intr_data_ptr
[0x35]);
91 PCI_INT(0x0, 0x14, 0x2, intr_data_ptr
[0x36]);
94 PCI_INT(0x0, 0x11, 0x0, intr_data_ptr
[0x40]);
95 PCI_INT(0x0, 0x11, 0x0, intr_data_ptr
[0x41]);
97 /* on board NIC & Slot PCIE. */
100 struct device
*dev
= pcidev_on_root(0x14, 4);
101 if (dev
&& dev
->enabled
) {
102 u8 bus_pci
= dev
->link_list
->secondary
;
104 PCI_INT(bus_pci
, 0x5, 0x0, 0x14);
105 PCI_INT(bus_pci
, 0x5, 0x1, 0x15);
106 PCI_INT(bus_pci
, 0x5, 0x2, 0x16);
107 PCI_INT(bus_pci
, 0x5, 0x3, 0x17);
110 PCI_INT(bus_pci
, 0x6, 0x0, 0x15);
111 PCI_INT(bus_pci
, 0x6, 0x1, 0x16);
112 PCI_INT(bus_pci
, 0x6, 0x2, 0x17);
113 PCI_INT(bus_pci
, 0x6, 0x3, 0x14);
116 PCI_INT(bus_pci
, 0x7, 0x0, 0x16);
117 PCI_INT(bus_pci
, 0x7, 0x1, 0x17);
118 PCI_INT(bus_pci
, 0x7, 0x2, 0x14);
119 PCI_INT(bus_pci
, 0x7, 0x3, 0x15);
123 PCI_INT(0x0, 0x06, 0x0, 0x13);
126 PCI_INT(0x0, 0x15, 0x0, 0x10);
128 PCI_INT(0x0, 0x15, 0x1, 0x11);
130 PCI_INT(0x0, 0x15, 0x2, 0x12);
132 PCI_INT(0x0, 0x15, 0x3, 0x13);
134 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
135 IO_LOCAL_INT(mp_ExtINT
, 0, MP_APIC_ALL
, 0x0);
136 IO_LOCAL_INT(mp_NMI
, 0, MP_APIC_ALL
, 0x1);
137 /* There is no extension information... */
139 /* Compute the checksums */
140 return mptable_finalize(mc
);
143 unsigned long write_smp_table(unsigned long addr
)
146 v
= smp_write_floating_table(addr
, 0);
147 return (unsigned long)smp_write_config_table(v
);