soc/intel/xeon_sp/spr: Create CXL ACPI resources only for
[coreboot.git] / src / include / stddef.h
blob82d38c39972f8147d30d487833c10af6e6748700
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef STDDEF_H
4 #define STDDEF_H
6 #include <commonlib/helpers.h>
8 typedef __PTRDIFF_TYPE__ ptrdiff_t;
9 typedef __SIZE_TYPE__ size_t;
10 #define SIZE_MAX __SIZE_MAX__
11 /* There is a GCC macro for a size_t type, but not
12 * for a ssize_t type. Below construct tricks GCC
13 * into making __SIZE_TYPE__ signed.
15 #define unsigned signed
16 typedef __SIZE_TYPE__ ssize_t;
17 #undef unsigned
19 typedef __WCHAR_TYPE__ wchar_t;
20 typedef __WINT_TYPE__ wint_t;
22 #define NULL ((void *)0)
24 /* The devicetree data structures are only mutable in ramstage. All other
25 stages have a constant devicetree. */
26 #if !ENV_PAYLOAD_LOADER
27 #define DEVTREE_EARLY 1
28 #else
29 #define DEVTREE_EARLY 0
30 #endif
32 #if DEVTREE_EARLY
33 #define DEVTREE_CONST const
34 #else
35 #define DEVTREE_CONST
36 #endif
38 /* Provide a pointer to address 0 that thwarts any "accessing this is
39 * undefined behaviour and do whatever" trickery in compilers.
40 * Use when you _really_ need to read32(zeroptr) (ie. read address 0).
42 extern char zeroptr[];
44 #endif /* STDDEF_H */