1 ## SPDX-License-Identifier: GPL-2.0-only
3 mainmenu "coreboot configuration"
12 string "Local version string"
14 Append an extra string to the end of the coreboot version.
16 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
21 config CONFIGURABLE_CBFS_PREFIX
24 Select this to prompt to use to configure the prefix for cbfs files.
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
31 config CBFS_PREFIX_FALLBACK
34 config CBFS_PREFIX_NORMAL
37 config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
43 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
50 config DEFAULT_COMPILER_LLVM_CLANG
53 Allows to override the default compiler. This can for instance be
54 set in site-local/Kconfig.
57 prompt "Compiler to use"
58 default COMPILER_LLVM_CLANG if DEFAULT_COMPILER_LLVM_CLANG
61 This option allows you to select the compiler used for building
63 You must build the coreboot crosscompiler for the board that you
66 To build all the GCC crosscompilers (takes a LONG time), run:
69 For help on individual architectures, run the command:
75 Use the GNU Compiler Collection (GCC) to build coreboot.
77 For details see http://gcc.gnu.org.
79 config COMPILER_LLVM_CLANG
81 depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG
83 Use LLVM/clang to build coreboot. To use this, you must build the
84 coreboot version of the clang compiler. Run the command
86 Note that Clang is not currently working on all architectures.
88 For details see http://clang.llvm.org.
92 config ARCH_SUPPORTS_CLANG
95 Opt-in flag for architectures that generally work well with CLANG.
96 By default the option would be hidden.
98 config ALLOW_EXPERIMENTAL_CLANG
99 bool "Allow experimental LLVM/Clang"
100 depends on !ARCH_SUPPORTS_CLANG
102 On some architectures CLANG does not work that well.
103 Use this only to try to get CLANG working.
106 bool "Allow building with any toolchain"
109 Many toolchains break when building coreboot since it uses quite
110 unusual linker features. Unless developers explicitly request it,
111 we'll have to assume that they use their distro compiler by mistake.
112 Make sure that using patched compilers is a conscious decision.
115 bool "Use ccache to speed up (re)compilation"
118 Enables the use of ccache for faster builds.
120 Requires the ccache utility in your system $PATH.
122 For details see https://ccache.samba.org.
125 bool "Test platform with include-what-you-use"
127 This runs each source file through the include-what-you-use tool
128 to check the header includes.
131 bool "Generate flashmap descriptor parser using flex and bison"
134 Enable this option if you are working on the flashmap descriptor
135 parser and made changes to fmd_scanner.l or fmd_parser.y.
137 Otherwise, say N to use the provided pregenerated scanner/parser.
139 config UTIL_GENPARSER
140 bool "Generate parsers for bincfg, sconfig and kconfig locally"
143 Enable this option if you are working on the sconfig device tree
144 parser or bincfg and made changes to the .l or .y files.
146 Otherwise, say N to use the provided pregenerated scanner/parser.
149 prompt "Option backend to use"
150 default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
151 default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
152 default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \
153 PAYLOAD_EDK2 && SMMSTORE_V2
155 config OPTION_BACKEND_NONE
158 config USE_OPTION_TABLE
159 bool "Use CMOS for configuration values"
160 depends on HAVE_OPTION_TABLE
162 Enable this option if coreboot shall read options from the "CMOS"
163 NVRAM instead of using hard-coded values.
165 config USE_UEFI_VARIABLE_STORE
166 bool "Use UEFI variable-store in SPI flash as option backend"
167 depends on DRIVERS_EFI_VARIABLE_STORE
168 depends on SMMSTORE_V2
170 Enable this option if coreboot shall read/write options from the
171 SMMSTORE region within the SPI flash. The region must be formatted
172 by the payload first before it can be used.
174 config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND
175 bool "Use mainboard-specific option backend"
176 depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
178 Use a mainboard-specific mechanism to access runtime-configurable
183 config STATIC_OPTION_TABLE
184 bool "Load default configuration values into CMOS on each boot"
185 depends on USE_OPTION_TABLE
187 Enable this option to reset "CMOS" NVRAM values to default on
188 every boot. Use this if you want the NVRAM configuration to
189 never be modified from its default values.
191 config MB_COMPRESS_RAMSTAGE_LZ4
194 Select this in a mainboard to use LZ4 compression by default
197 prompt "Ramstage compression"
198 depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
199 default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
200 default COMPRESS_RAMSTAGE_LZMA
202 config COMPRESS_RAMSTAGE_LZMA
203 bool "Compress ramstage with LZMA"
205 Compress ramstage with LZMA to save memory in the flash image.
207 config COMPRESS_RAMSTAGE_LZ4
208 bool "Compress ramstage with LZ4"
210 LZ4 doesn't give as good compression as LZMA, but decompresses much
211 faster. For large binaries such as ramstage, it's typically best to
212 use LZMA, but there can be cases where the faster decompression of
213 LZ4 can lead to a faster boot time. Testing on each individual board
214 is typically going to be needed due to the large number of factors
215 that can influence the decision. Binary size, CPU speed, ROM read
216 speed, cache, and other factors all play a part.
218 If you're not sure, stick with LZMA.
222 config COMPRESS_PRERAM_STAGES
223 bool "Compress romstage and verstage with LZ4"
224 depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
225 # Default value set at the end of the file
227 Compress romstage and (if it exists) verstage with LZ4 to save flash
228 space and speed up boot, since the time for reading the image from SPI
229 (and in the vboot case verifying it) is usually much greater than the
230 time spent decompressing. Doesn't work for XIP stages for obvious
233 config COMPRESS_BOOTBLOCK
235 depends on HAVE_BOOTBLOCK
237 This option can be used to compress the bootblock with LZ4 and attach
238 a small self-decompression stub to its front. This can drastically
239 reduce boot time on platforms where the bootblock is loaded over a
240 very slow connection and bootblock size trumps all other factors for
241 speed. Since using this option usually requires changes to the
242 SoC memlayout and possibly extra support code, it should not be
243 user-selectable. (There's no real point in offering this to the user
244 anyway... if it works and saves boot time, you would always want it.)
246 config SEPARATE_ROMSTAGE
247 bool "Build a separate romstage"
250 Build a separate romstage that is loaded by bootblock. With this
251 option disabled the romstage sources are linked inside the bootblock
254 config INCLUDE_CONFIG_FILE
255 bool "Include the coreboot .config file into the ROM image"
256 # Default value set at the end of the file
258 Include the .config file that was used to compile coreboot
259 in the (CBFS) ROM image. This is useful if you want to know which
260 options were used to build a specific coreboot.rom image.
262 Saying Y here will increase the image size by 2-3KB.
264 You can then use cbfstool to extract the config from a final image:
266 cbfstool coreboot.rom extract -n config -f <output file path>
268 Alternatively, you can also use cbfstool to print the image
269 contents (including the raw 'config' item we're looking for).
273 $ cbfstool coreboot.rom print
274 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
278 Name Offset Type Size
279 cmos_layout.bin 0x0 CMOS layout 1159
280 fallback/romstage 0x4c0 stage 339756
281 fallback/ramstage 0x53440 stage 186664
282 fallback/payload 0x80dc0 payload 51526
283 config 0x8d740 raw 3324
284 (empty) 0x8e480 null 3610440
286 config COLLECT_TIMESTAMPS
287 bool "Create a table of timestamps collected during boot"
288 default y if ARCH_X86
290 Make coreboot create a table of timer-ID/timer-value pairs to
291 allow measuring time spent at different phases of the boot process.
293 config TIMESTAMPS_ON_CONSOLE
294 bool "Print the timestamp values on the console"
296 depends on COLLECT_TIMESTAMPS
298 Print the timestamps to the debug console if enabled at level info.
301 bool "Allow use of binary-only repository"
304 This draws in the blobs repository, which contains binary files that
305 might be required for some chipsets or boards.
306 This flag ensures that a "Free" option remains available for users.
309 bool "Allow AMD blobs repository (with license agreement)"
312 This draws in the amd_blobs repository, which contains binary files
313 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
314 etc. Selecting this item to download or clone the repo implies your
315 agreement to the AMD license agreement. A copy of the license text
316 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
317 and your copy of the license is present in the repo once downloaded.
319 Note that for some products, omitting PSP, SMU images, or other items
320 may result in a nonbooting coreboot.rom.
323 bool "Allow QC blobs repository (selecting this agrees to the license!)"
326 This draws in the qc_blobs repository, which contains binary files
327 distributed by Qualcomm that are required to build firmware for
328 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
329 firmware). If you say Y here you are implicitly agreeing to the
330 Qualcomm license agreement which can be found at:
331 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
333 *****************************************************
334 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
335 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
336 *****************************************************
338 Not selecting this option means certain Qualcomm SoCs and related
339 mainboards cannot be built and will be hidden from the "Mainboards"
343 bool "Code coverage support"
344 depends on COMPILER_GCC
346 Add code coverage support for coreboot. This will store code
347 coverage information in CBMEM for extraction from user space.
351 bool "Undefined behavior sanitizer support"
354 Instrument the code with checks for undefined behavior. If unsure,
355 say N because it adds a small performance penalty and may abort
356 on code that happens to work in spite of the UB.
358 config HAVE_ASAN_IN_ROMSTAGE
362 config ASAN_IN_ROMSTAGE
366 Enable address sanitizer in romstage for platform.
368 config HAVE_ASAN_IN_RAMSTAGE
372 config ASAN_IN_RAMSTAGE
376 Enable address sanitizer in ramstage for platform.
379 bool "Address sanitizer support"
381 select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
382 select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
383 depends on COMPILER_GCC
385 Enable address sanitizer - runtime memory debugger,
386 designed to find out-of-bounds accesses and use-after-scope bugs.
388 This feature consumes up to 1/8 of available memory and brings about
389 ~1.5x performance slowdown.
394 comment "Before using this feature, make sure that "
395 comment "asan_shadow_offset_callback patch is applied to GCC."
399 prompt "Stage Cache for ACPI S3 resume"
400 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE
401 default TSEG_STAGE_CACHE if SMM_TSEG
403 config NO_STAGE_CACHE
406 Do not save any component in stage cache for resume path. On resume,
407 all components would be read back from CBFS again.
409 config TSEG_STAGE_CACHE
413 The option enables stage cache support for platform. Platform
414 can stash copies of postcar, ramstage and raw runtime data
415 inside SMM TSEG, to be restored on S3 resume path.
417 config CBMEM_STAGE_CACHE
421 The option enables stage cache support for platform. Platform
422 can stash copies of postcar, ramstage and raw runtime data
425 While the approach is faster than reloading stages from boot media
426 it is also a possible attack scenario via which OS can possibly
427 circumvent SMM locks and SPI write protections.
429 If unsure, select 'N'
433 config MAINBOARD_DISABLE_STAGE_CACHE
436 Selected by mainboards which wish to disable the stage cache.
437 E.g. mainboards which don't use S3 resume in the field may wish to
438 disable it to save boot time at the cost of increasing S3 resume time.
441 bool "Update existing coreboot.rom image"
443 If this option is enabled, no new coreboot.rom file
444 is created. Instead it is expected that there already
445 is a suitable file for further processing.
446 The bootblock will not be modified.
448 If unsure, select 'N'
450 config BOOTSPLASH_IMAGE
451 bool "Add a bootsplash image"
453 Select this option if you have a bootsplash image that you would
454 like to add to your ROM.
456 This will only add the image to the ROM. To actually run it check
457 options under 'Display' section.
459 config BOOTSPLASH_FILE
460 string "Bootsplash path and filename"
461 depends on BOOTSPLASH_IMAGE
462 # Default value set at the end of the file
464 The path and filename of the file to use as graphical bootsplash
465 screen. The file format has to be JPEG with YCC 4:2:0 color sampling
466 unless converted with "Pre-process bootsplash file with ImageMagick".
468 The image can only be displayed by coreboot if it's smaller or has
469 the same size as the framebuffer resolution. Width and height have
470 to be a multiple of 16 pixels.
472 Setting these constraints allows a leaner implementation in coreboot.
473 The minimum necessary ImageMagick command line seems to be:
474 $ convert input.img -colorspace YCC -sampling-factor 4:2:0 bootsplash.jpg
476 config BOOTSPLASH_CONVERT
477 bool "Pre-process bootsplash file with ImageMagick"
478 depends on BOOTSPLASH_IMAGE
480 Use ImageMagick (`convert` program) to convert a bootsplash image
481 to the supported JPEG format.
483 config BOOTSPLASH_CONVERT_QUALITY
484 int "Bootsplash JPEG target quality (%)"
485 depends on BOOTSPLASH_CONVERT
487 # Default value set at the end of the file
489 config BOOTSPLASH_CONVERT_RESIZE
490 bool "Resize bootsplash image"
491 depends on BOOTSPLASH_CONVERT
493 Resize the image to the given resolution. Aspect ratio will be kept,
494 adding black bars as necessary.
496 config BOOTSPLASH_CONVERT_RESOLUTION
497 string "Bootsplash image target size"
498 depends on BOOTSPLASH_CONVERT_RESIZE
499 # Default value set at the end of the file
501 Target image resolution given as <width>x<height>, e.g. 1024x768.
502 Values not divisible by 16 will be rounded down.
504 When using coreboot to display the bootsplash image (CONFIG_BOOTSPLASH),
505 set this lower or equal to the minimum resolution you expect.
507 config BOOTSPLASH_CONVERT_COLORSWAP
508 bool "Swap red and blue color channels"
509 depends on BOOTSPLASH_CONVERT
511 The JPEG decoder currently ignores the framebuffer color order.
512 If your colors seem all wrong, try this option.
515 bool "Firmware Configuration Probing"
518 Enable support for probing devices with fw_config. This is a simple
519 bitmask broken into fields and options for probing.
521 config FW_CONFIG_SOURCE_CHROMEEC_CBI
522 bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
523 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
526 This option tells coreboot to read the firmware configuration value
527 from the Google Chrome Embedded Controller CBI interface. This source
528 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
531 config FW_CONFIG_SOURCE_CBFS
532 bool "Obtain Firmware Configuration value from CBFS"
536 With this option enabled coreboot will look for the 32bit firmware
537 configuration value in CBFS at the selected prefix with the file name
538 "fw_config". This option will override other sources and allow the
539 local image to preempt the mainboard selected source and can be used as
540 FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option.
542 config FW_CONFIG_SOURCE_VPD
543 bool "Obtain Firmware Configuration value from VPD"
544 depends on FW_CONFIG && VPD
547 With this option enabled coreboot will look for the 32bit firmware
548 configuration value in VPD key name "fw_config". This option will
549 override other sources and allow the local image to preempt the mainboard
550 selected source and can be used for other FW_CONFIG_SOURCEs fallback option.
552 config HAVE_RAMPAYLOAD
556 bool "Enable coreboot flow without executing ramstage"
557 default y if ARCH_X86
558 depends on HAVE_RAMPAYLOAD
560 If this option is enabled, coreboot flow will skip ramstage
561 loading and execution of ramstage to load payload.
563 Instead it is expected to load payload from postcar stage itself.
565 In this flow coreboot will perform basic x86 initialization
566 (DRAM resource allocation), MTRR programming,
567 Skip PCI enumeration logic and only allocate BAR for fixed devices
568 (bootable devices, TPM over GSPI).
570 config HAVE_CONFIGURABLE_RAMSTAGE
573 config CONFIGURABLE_RAMSTAGE
574 bool "Enable a configurable ramstage."
575 default y if ARCH_X86
576 depends on HAVE_CONFIGURABLE_RAMSTAGE
578 A configurable ramstage allows you to select which parts of the ramstage
579 to run. Currently, we can only select a minimal PCI scanning step.
580 The minimal PCI scanning will only check those parts that are enabled
581 in the devicetree.cb. By convention none of those devices should be bridges.
583 config MINIMAL_PCI_SCANNING
584 bool "Enable minimal PCI scanning"
585 depends on CONFIGURABLE_RAMSTAGE && PCI
587 If this option is enabled, coreboot will scan only PCI devices
588 marked as mandatory in devicetree.cb
590 menu "Software Bill Of Materials (SBOM)"
592 source "src/sbom/Kconfig"
599 source "src/mainboard/Kconfig"
603 default "devicetree.cb"
605 This symbol allows mainboards to select a different file under their
606 mainboard directory for the devicetree.cb file. This allows the board
607 variants that need different devicetrees to be in the same directory.
609 Examples: "devicetree.variant.cb"
610 "variant/devicetree.cb"
612 config OVERRIDE_DEVICETREE
616 This symbol allows variants to provide an override devicetree file to
617 override the registers and/or add new devices on top of the ones
618 provided by baseboard devicetree using CONFIG_DEVICETREE.
620 Examples: "devicetree.variant-override.cb"
621 "variant/devicetree-override.cb"
624 string "fmap description file in fmd format"
625 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
628 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
629 but in some cases more complex setups are required.
630 When an fmd is specified, it overrides the default format.
633 hex "Size of CBFS filesystem in ROM"
634 depends on FMDFILE = ""
635 # Default value set at the end of the file
637 This is the part of the ROM actually managed by CBFS, located at the
638 end of the ROM (passed through cbfstool -o) on x86 and at the start
639 of the ROM (passed through cbfstool -s) everywhere else. It defaults
640 to span the whole ROM on all but Intel systems that use an Intel Firmware
641 Descriptor. It can be overridden to make coreboot live alongside other
642 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
643 binaries. This symbol should only be used to generate a default FMAP and
644 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
648 # load site-local kconfig to allow user specific defaults and overrides
649 source "site-local/Kconfig"
651 config SYSTEM_TYPE_LAPTOP
655 config SYSTEM_TYPE_TABLET
659 config SYSTEM_TYPE_DETACHABLE
663 config SYSTEM_TYPE_CONVERTIBLE
667 config CBFS_AUTOGEN_ATTRIBUTES
671 If this option is selected, every file in cbfs which has a constraint
672 regarding position or alignment will get an additional file attribute
673 which describes this constraint.
678 source "src/soc/*/*/Kconfig"
679 source "src/soc/*/*/Kconfig.common"
681 source "src/cpu/Kconfig"
682 comment "Northbridge"
683 source "src/northbridge/*/*/Kconfig"
684 source "src/northbridge/*/*/Kconfig.common"
685 comment "Southbridge"
686 source "src/southbridge/*/*/Kconfig"
687 source "src/southbridge/*/*/Kconfig.common"
689 source "src/superio/*/*/Kconfig"
690 comment "Embedded Controllers"
691 source "src/ec/acpi/Kconfig"
692 source "src/ec/*/*/Kconfig"
694 source "src/southbridge/intel/common/firmware/Kconfig"
695 source "src/vendorcode/*/Kconfig"
697 source "src/arch/*/Kconfig"
699 config CHIPSET_DEVICETREE
703 This symbol allows a chipset to provide a set of default settings in
704 a devicetree which are common to all mainboards. This may include
705 devices (including alias names), chip drivers, register settings,
706 and others. This path is relative to the src/ directory.
708 Example: "chipset.cb"
712 source "src/device/Kconfig"
714 menu "Generic Drivers"
715 source "src/drivers/*/Kconfig"
716 source "src/drivers/*/*/Kconfig"
717 source "src/drivers/*/*/*/Kconfig"
718 source "src/commonlib/storage/Kconfig"
723 source "src/security/Kconfig"
724 source "src/vendorcode/eltan/security/Kconfig"
728 source "src/acpi/Kconfig"
730 # This option is for the current boards/chipsets where SPI flash
731 # is not the boot device. Currently nearly all boards/chipsets assume
732 # SPI flash is the boot device.
733 config BOOT_DEVICE_NOT_SPI_FLASH
737 config BOOT_DEVICE_SPI_FLASH
739 default y if !BOOT_DEVICE_NOT_SPI_FLASH
742 config BOOT_DEVICE_MEMORY_MAPPED
744 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
747 Inform system if SPI is memory-mapped or not.
749 config BOOT_DEVICE_SUPPORTS_WRITES
753 Indicate that the platform has writable boot device
766 default 0x2000 if ARCH_X86
773 source "src/console/Kconfig"
775 config ACPI_S1_NOT_SUPPORTED
779 Set this to 'y' on platforms that do not support ACPI S1 state.
781 config HAVE_ACPI_RESUME
785 config DISABLE_ACPI_HIBERNATE
789 Removes S4 from the available sleepstates
791 config RESUME_PATH_SAME_AS_BOOT
793 default y if ARCH_X86
794 depends on HAVE_ACPI_RESUME
796 This option indicates that when a system resumes it takes the
797 same path as a regular boot. e.g. an x86 system runs from the
798 reset vector at 0xfffffff0 on both resume and warm/cold boot.
800 config NO_MONOTONIC_TIMER
803 config HAVE_MONOTONIC_TIMER
805 depends on !NO_MONOTONIC_TIMER
808 The board/chipset provides a monotonic timer.
810 config GENERIC_UDELAY
812 depends on HAVE_MONOTONIC_TIMER
813 default y if !ARCH_X86
815 The board/chipset uses a generic udelay function utilizing the
820 depends on HAVE_MONOTONIC_TIMER
822 Provide a timer queue for performing time-based callbacks.
824 config COOP_MULTITASKING
829 Cooperative multitasking allows callbacks to be multiplexed on the
830 main thread. With this enabled it allows for multiple execution paths
831 to take place when they have udelay() calls within their code.
836 depends on COOP_MULTITASKING
838 How many execution threads to cooperatively multitask with.
840 config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
843 Selected by mainboards which implement a mainboard-specific mechanism
844 to access the values for runtime-configurable options. For example, a
845 custom BMC interface or an EEPROM with an externally-imposed layout.
847 config HAVE_OPTION_TABLE
851 This variable specifies whether a given board has a cmos.layout
852 file containing NVRAM/CMOS bit definitions.
853 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
855 config CMOS_LAYOUT_FILE
857 default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout"
858 depends on HAVE_OPTION_TABLE
860 config PCI_IO_CFG_EXT
869 config USE_WATCHDOG_ON_BOOT
877 Enable Unified Memory Architecture for graphics.
882 This variable specifies whether a given board has MP table support.
883 It is usually set in mainboard/*/Kconfig.
884 Whether or not the MP table is actually generated by coreboot
885 is configurable by the user via GENERATE_MP_TABLE.
887 config HAVE_PIRQ_TABLE
890 This variable specifies whether a given board has PIRQ table support.
891 It is usually set in mainboard/*/Kconfig.
892 Whether or not the PIRQ table is actually generated by coreboot
893 is configurable by the user via GENERATE_PIRQ_TABLE.
899 Build support for NHLT (non HD Audio) ACPI table generation.
901 #These Options are here to avoid "undefined" warnings.
902 #The actual selection and help texts are in the following menu.
906 config GENERATE_MP_TABLE
907 prompt "Generate an MP table" if HAVE_MP_TABLE
909 depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256
910 default HAVE_MP_TABLE
912 Generate an MP table (conforming to the Intel MultiProcessor
913 specification 1.4) for this board.
917 config GENERATE_PIRQ_TABLE
918 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
920 default HAVE_PIRQ_TABLE
922 Generate a PIRQ table for this board.
926 config GENERATE_SMBIOS_TABLES
928 bool "Generate SMBIOS tables"
931 Generate SMBIOS tables for this board.
935 config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
939 If enabled, only generate SMBIOS Type 41 entries for PCI devices in
940 the devicetree for which Type 41 information is provided, e.g. with
941 the `smbios_dev_info` devicetree syntax. This is useful to manually
942 assign specific instance IDs to onboard devices irrespective of the
943 device traversal order. It is assumed that instance IDs for devices
944 of the same class are unique.
945 When disabled, coreboot autogenerates SMBIOS Type 41 entries for all
946 appropriate PCI devices in the devicetree. Instance IDs are assigned
947 successive numbers from a monotonically increasing counter, with one
948 counter for each device class.
950 config SMBIOS_PROVIDED_BY_MOBO
954 if GENERATE_SMBIOS_TABLES
957 prompt "SMBIOS BIOS Vendor name"
961 The BIOS Vendor name to store in the SMBIOS Type0 table.
963 config MAINBOARD_SERIAL_NUMBER
964 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
968 The Serial Number to store in SMBIOS structures.
970 config MAINBOARD_VERSION
971 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
975 The Version Number to store in SMBIOS structures.
977 config MAINBOARD_SMBIOS_MANUFACTURER
978 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
980 default MAINBOARD_VENDOR
982 Override the default Manufacturer stored in SMBIOS structures.
984 config MAINBOARD_SMBIOS_PRODUCT_NAME
985 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
987 default MAINBOARD_PART_NUMBER
989 Override the default Product name stored in SMBIOS structures.
991 config VPD_SMBIOS_VERSION
992 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
996 Selecting this option will read firmware_version from
997 VPD_RO and override SMBIOS type 0 version. One special
998 scenario of using this feature is to assign a BIOS version
999 to a coreboot image without the need to rebuild from source.
1005 source "payloads/Kconfig"
1009 comment "CPU Debug Settings"
1010 source "src/cpu/*/Kconfig.debug_cpu"
1012 comment "Vendorcode Debug Settings"
1013 source "src/vendorcode/*/*/Kconfig.debug"
1015 comment "BLOB Debug Settings"
1016 source "src/drivers/intel/fsp*/Kconfig.debug_blob"
1018 comment "General Debug Settings"
1020 # TODO: Better help text and detailed instructions.
1022 bool "GDB debugging support"
1024 depends on DRIVERS_UART
1026 If enabled, you will be able to set breakpoints for gdb debugging.
1027 See src/arch/x86/c_start.S for details.
1030 bool "Wait for a GDB connection in the ramstage"
1034 If enabled, coreboot will wait for a GDB connection in the ramstage.
1037 config FATAL_ASSERTS
1038 bool "Halt when hitting a BUG() or assertion error"
1041 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
1043 config HAVE_DEBUG_GPIO
1047 bool "Output verbose GPIO debug messages"
1048 depends on HAVE_DEBUG_GPIO
1051 bool "Output verbose CBFS debug messages"
1054 This option enables additional CBFS related debug messages.
1056 config HAVE_DEBUG_RAM_SETUP
1059 config DEBUG_RAM_SETUP
1060 bool "Output verbose RAM init debug messages"
1062 depends on HAVE_DEBUG_RAM_SETUP
1064 This option enables additional RAM init related debug messages.
1065 It is recommended to enable this when debugging issues on your
1066 board which might be RAM init related.
1068 Note: This option will increase the size of the coreboot image.
1073 bool "Check PIRQ table consistency"
1075 depends on GENERATE_PIRQ_TABLE
1079 config HAVE_DEBUG_SMBUS
1083 bool "Output verbose SMBus debug messages"
1085 depends on HAVE_DEBUG_SMBUS
1087 This option enables additional SMBus (and SPD) debug messages.
1089 Note: This option will increase the size of the coreboot image.
1094 bool "Output verbose SMI debug messages"
1096 depends on HAVE_SMI_HANDLER
1097 select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH
1099 This option enables additional SMI related debug messages.
1101 Note: This option will increase the size of the coreboot image.
1105 config DEBUG_PERIODIC_SMI
1106 bool "Trigger SMI periodically"
1107 depends on DEBUG_SMI
1109 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
1110 # printk(BIOS_DEBUG, ...) calls.
1112 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1116 This option enables additional malloc related debug messages.
1118 Note: This option will increase the size of the coreboot image.
1122 # Only visible if DEBUG_SPEW (8) is set.
1123 config DEBUG_RESOURCES
1124 bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1127 This option enables additional PCI memory and IO debug messages.
1128 Note: This option will increase the size of the coreboot image.
1131 config DEBUG_CONSOLE_INIT
1132 bool "Debug console initialisation code"
1135 With this option printk()'s are attempted before console hardware
1136 initialisation has been completed. Your mileage may vary.
1138 Typically you will need to modify source in console_hw_init() such
1139 that a working console appears before the one you want to debug.
1143 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
1144 # printk(BIOS_DEBUG, ...) calls.
1145 config REALMODE_DEBUG
1146 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1149 depends on PCI_OPTION_ROM_RUN_REALMODE
1151 This option enables additional x86emu related debug messages.
1153 Note: This option will increase the time to emulate a ROM.
1158 bool "Output verbose x86emu debug messages"
1160 depends on PCI_OPTION_ROM_RUN_YABEL
1162 This option enables additional x86emu related debug messages.
1164 Note: This option will increase the size of the coreboot image.
1170 config X86EMU_DEBUG_JMP
1171 bool "Trace JMP/RETF"
1174 Print information about JMP and RETF opcodes from x86emu.
1176 Note: This option will increase the size of the coreboot image.
1180 config X86EMU_DEBUG_TRACE
1181 bool "Trace all opcodes"
1184 Print _all_ opcodes that are executed by x86emu.
1186 WARNING: This will produce a LOT of output and take a long time.
1188 Note: This option will increase the size of the coreboot image.
1192 config X86EMU_DEBUG_PNP
1193 bool "Log Plug&Play accesses"
1196 Print Plug And Play accesses made by option ROMs.
1198 Note: This option will increase the size of the coreboot image.
1202 config X86EMU_DEBUG_DISK
1206 Print Disk I/O related messages.
1208 Note: This option will increase the size of the coreboot image.
1212 config X86EMU_DEBUG_PMM
1216 Print messages related to POST Memory Manager (PMM).
1218 Note: This option will increase the size of the coreboot image.
1223 config X86EMU_DEBUG_VBE
1224 bool "Debug VESA BIOS Extensions"
1227 Print messages related to VESA BIOS Extension (VBE) functions.
1229 Note: This option will increase the size of the coreboot image.
1233 config X86EMU_DEBUG_INT10
1234 bool "Redirect INT10 output to console"
1237 Let INT10 (i.e. character output) calls print messages to debug output.
1239 Note: This option will increase the size of the coreboot image.
1243 config X86EMU_DEBUG_INTERRUPTS
1244 bool "Log intXX calls"
1247 Print messages related to interrupt handling.
1249 Note: This option will increase the size of the coreboot image.
1253 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1254 bool "Log special memory accesses"
1257 Print messages related to accesses to certain areas of the virtual
1258 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1260 Note: This option will increase the size of the coreboot image.
1264 config X86EMU_DEBUG_MEM
1265 bool "Log all memory accesses"
1268 Print memory accesses made by option ROM.
1269 Note: This also includes accesses to fetch instructions.
1271 Note: This option will increase the size of the coreboot image.
1275 config X86EMU_DEBUG_IO
1276 bool "Log IO accesses"
1279 Print I/O accesses made by option ROM.
1281 Note: This option will increase the size of the coreboot image.
1285 config X86EMU_DEBUG_TIMINGS
1286 bool "Output timing information"
1288 depends on HAVE_MONOTONIC_TIMER
1290 Print timing information needed by i915tool.
1296 config DEBUG_SPI_FLASH
1297 bool "Output verbose SPI flash debug messages"
1299 depends on SPI_FLASH
1301 This option enables additional SPI flash related debug messages.
1304 bool "Output verbose IPMI debug messages"
1308 This option enables additional IPMI related debug messages.
1310 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1311 # Only visible with the right southbridge and loglevel.
1312 config DEBUG_INTEL_ME
1313 bool "Verbose logging for Intel Management Engine"
1316 Enable verbose logging for Intel Management Engine driver that
1317 is present on Intel 6-series chipsets.
1321 bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1324 This option enables additional function entry and exit debug messages
1325 for select functions.
1326 Note: This option will increase the size of the coreboot image.
1329 config DEBUG_COVERAGE
1330 bool "Debug code coverage"
1334 If enabled, the code coverage hooks in coreboot will output some
1335 information about the coverage data that is dumped.
1337 config DEBUG_BOOT_STATE
1338 bool "Debug boot state machine"
1341 Control debugging of the boot state machine. When selected displays
1342 the state boundaries in ramstage.
1344 config DEBUG_ADA_CODE
1345 bool "Compile debug code in Ada sources"
1348 Add the compiler switch `-gnata` to compile code guarded by
1351 config HAVE_EM100_SUPPORT
1354 This is enabled by platforms which can support using the EM100.
1357 bool "Configure image for EM100 usage"
1358 depends on HAVE_EM100_SUPPORT
1360 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1361 over USB. However it only supports a maximum SPI clock of 20MHz and
1362 single data output. Enable this option to use a 20MHz SPI clock and
1363 disable "Dual Output Fast Read" Support.
1365 On AMD platforms this changes the SPI speed at run-time if the
1366 mainboard code supports this. On supported Intel platforms this works
1367 by changing the settings in the descriptor.bin file.
1369 config DEBUG_ACPICA_COMPATIBLE
1370 bool "Print out ACPI tables in ACPICA compatible format"
1371 depends on HAVE_ACPI_TABLES
1373 Select this to print out ACPI tables in an ACPICA compatible
1374 format. Set the console loglevel to verbosity 'SPEW'.
1375 To analyze ACPI tables capture the coreboot log between
1376 "Printing ACPI in ACPICA compatible table" and "Done printing
1377 ACPI in ACPICA compatible table".
1378 Remove the prefix "[SPEW ] " and then issue 'acpixtract -a dump'
1379 to extract all the tables. Then use 'iasl -d' on the .dat files
1380 to decompile the tables.
1384 ###############################################################################
1385 # Set variables with no prompt - these can be set anywhere, and putting at
1386 # the end of this file gives the most flexibility.
1388 source "src/lib/Kconfig"
1390 config WARNINGS_ARE_ERRORS
1394 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1395 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1396 # mutually exclusive. One of these options must be selected in the
1397 # mainboard Kconfig if the chipset supports enabling and disabling of
1398 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1399 # in mainboard/Kconfig to know if the button should be enabled or not.
1401 config POWER_BUTTON_DEFAULT_ENABLE
1404 Select when the board has a power button which can optionally be
1405 disabled by the user.
1407 config POWER_BUTTON_DEFAULT_DISABLE
1410 Select when the board has a power button which can optionally be
1411 enabled by the user, e.g. when the board ships with a jumper over
1412 the power switch contacts.
1414 config POWER_BUTTON_FORCE_ENABLE
1417 Select when the board requires that the power button is always
1420 config POWER_BUTTON_FORCE_DISABLE
1423 Select when the board requires that the power button is always
1424 disabled, e.g. when it has been hardwired to ground.
1426 config POWER_BUTTON_IS_OPTIONAL
1428 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1429 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1431 Internal option that controls ENABLE_POWER_BUTTON visibility.
1437 Internal option that controls whether we compile in register scripts.
1439 config MAX_REBOOT_CNT
1443 Internal option that sets the maximum number of bootblock executions allowed
1444 with the normal image enabled before assuming the normal image is defective
1445 and switching to the fallback image.
1447 config UNCOMPRESSED_RAMSTAGE
1450 config NO_XIP_EARLY_STAGES
1452 default n if ARCH_X86
1455 Identify if early stages are eXecute-In-Place(XIP).
1457 config EARLY_CBMEM_LIST
1461 Enable display of CBMEM during romstage and postcar.
1463 config RELOCATABLE_MODULES
1466 If RELOCATABLE_MODULES is selected then support is enabled for
1467 building relocatable modules in the RAM stage. Those modules can be
1468 loaded anywhere and all the relocations are handled automatically.
1470 config GENERIC_GPIO_LIB
1473 If enabled, compile the generic GPIO library. A "generic" GPIO
1474 implies configurability usually found on SoCs, particularly the
1475 ability to control internal pull resistors.
1477 config BOOTBLOCK_CUSTOM
1478 # To be selected by arch, SoC or mainboard if it does not want use the normal
1479 # src/lib/bootblock.c#main() C entry point.
1482 config BOOTBLOCK_IN_CBFS
1484 default y if ARCH_X86
1486 Select this on platforms that have a top aligned bootblock inside cbfs.
1488 config MEMLAYOUT_LD_FILE
1490 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
1492 This variable allows SoC/mainboard to supply in a custom linker file
1493 if required. This determines the linker file used for all the stages
1494 (bootblock, romstage, verstage, ramstage, postcar) in
1495 src/arch/${ARCH}/Makefile.mk.
1497 ###############################################################################
1498 # Set default values for symbols created before mainboards. This allows the
1499 # option to be displayed in the general menu, but the default to be loaded in
1500 # the mainboard if desired.
1501 config COMPRESS_PRERAM_STAGES
1502 depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
1505 config INCLUDE_CONFIG_FILE
1508 config BOOTSPLASH_FILE
1509 depends on BOOTSPLASH_IMAGE
1510 default "bootsplash.jpg"
1512 config BOOTSPLASH_CONVERT_QUALITY
1513 depends on BOOTSPLASH_CONVERT
1516 config BOOTSPLASH_CONVERT_RESOLUTION
1517 depends on BOOTSPLASH_CONVERT_RESIZE
1523 config HAVE_BOOTBLOCK
1527 config HAVE_VERSTAGE
1529 depends on VBOOT_SEPARATE_VERSTAGE
1532 config HAVE_ROMSTAGE
1534 depends on SEPARATE_ROMSTAGE
1537 config HAVE_RAMSTAGE
1539 default n if RAMPAYLOAD