src/northbridge/via/vx900/early_host_bus_ctl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012  Alexandru Gagniuc <mr.nuke.me@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <device/pci_ops.h>
  18
  19 #include "early_vx900.h"
  20
  21 static void vx900_cpu_bus_preram_setup(void)
  22 {
  23         /* Faster CPU to DRAM Cycle */
  24         pci_update_config8(HOST_BUS, 0x50, ~0x0f, 0x08);
  25         /* CPU Interface Control - Basic Options */
  26         pci_or_config8(HOST_BUS, 0x51, 0x6c);
  27         /*CPU Interface Control - Advanced Options */
  28         pci_write_config8(HOST_BUS, 0x52, 0xc7);
  29         /* Enable 8QW burst and 4QW request merging [4] and [2]
  30          * and special mode for read cycles bit[3] */
  31         pci_or_config8(HOST_BUS, 0x54, (1 << 4) | (1 << 2) | (1 << 3));
  32         /* High priority upstream requests on V4 bus */
  33         pci_write_config8(HOST_BUS, 0x56, 0x03);
  34         /* CPU to DRAM extra 1T access control */
  35         pci_or_config8(HOST_BUS, 0x59, (1 << 2));
  36         /* Queue reordering */
  37         pci_or_config8(HOST_BUS, 0x5f, (1 << 6));
  38         /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */
  39         pci_or_config8(HOST_BUS, 0x98, 0x60);
  40         /* 1T delay for data on CPU bus */
  41         pci_write_config8(HOST_BUS, 0x9e, 0x0e);
  42         /* Arbitrate ownership of DRAM controller a few cycles earlier */
  43         pci_or_config8(HOST_BUS, 0x9f, (1 << 7));
  44         /* Write retire policy */
  45         pci_write_config8(HOST_BUS, 0x5d, 0xa2);
  46         /* Occupancy timer */
  47         pci_write_config8(HOST_BUS, 0x53, 0x44);
  48         /* Medium Threshold for Write Retire Policy - 6 requests */
  49         pci_or_config8(HOST_BUS, 0x56, 0x60);
  50         /* Bandwidth timer */
  51         pci_write_config8(HOST_BUS, 0x5e, 0x44);
  52 }
  53
  54 /**
  55  * \brief Configure the CPU to northbridge bus (formerly, FSB)
  56  *
  57  * Configure the CPU <-> host interface. This interface is complex and needs to
  58  * be set up to operate properly. Configured parameters include bandwidth
  59  * arbitration. This function does not, however, change the physical interface
  60  * parameters, such as drive strength and signal timing. Instead, it assumes
  61  * that those parameters were already configured correctly from the ROMSTRAP.
  62  */
  63 void vx900_cpu_bus_interface_setup(void)
  64 {
  65         vx900_cpu_bus_preram_setup();
  66
  67         dump_pci_device(HOST_BUS);
  68 }