src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2018 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/byteorder.h>
  17 #include <cbfs.h>
  18 #include <console/console.h>
  19 #include <fsp/api.h>
  20 #include <soc/romstage.h>
  21 #include "spd/spd.h"
  22 #include <string.h>
  23 #include <spd_bin.h>
  24
  25 void mainboard_memory_init_params(FSPM_UPD *mupd)
  26 {
  27         FSP_M_CONFIG *mem_cfg;
  28         mem_cfg = &mupd->FspmConfig;
  29         u8 spd_index;
  30
  31         mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
  32         mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
  33         mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
  34         mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
  35         mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
  36         mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
  37
  38         mem_cfg->DqPinsInterleaved = 0;
  39         mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
  40         mem_cfg->ECT = 1; /* Early Command Training Enabled */
  41         spd_index = 2;
  42
  43         struct region_device spd_rdev;
  44
  45         if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
  46                 die("spd.bin not found\n");
  47
  48         mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
  49         /* Memory leak is ok since we have memory mapped boot media */
  50         mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
  51         mem_cfg->RefClk = 0; /* Auto Select CLK freq */
  52         mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
  53 }