src/soc/samsung/exynos5250/uart.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 Samsung Electronics
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <boot/coreboot_tables.h>
  18 #include <console/uart.h>
  19 #include <soc/clk.h>
  20 #include <soc/cpu.h>
  21 #include <soc/periph.h>
  22 #include <soc/uart.h>
  23 #include <types.h>
  24
  25 #define RX_FIFO_COUNT_MASK      0xff
  26 #define RX_FIFO_FULL_MASK       (1 << 8)
  27 #define TX_FIFO_FULL_MASK       (1 << 24)
  28
  29 #if 0
  30 /*
  31  * The coefficient, used to calculate the baudrate on S5P UARTs is
  32  * calculated as
  33  * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
  34  * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
  35  * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
  36  */
  37 static const int udivslot[] = {
  38         0,
  39         0x0080,
  40         0x0808,
  41         0x0888,
  42         0x2222,
  43         0x4924,
  44         0x4a52,
  45         0x54aa,
  46         0x5555,
  47         0xd555,
  48         0xd5d5,
  49         0xddd5,
  50         0xdddd,
  51         0xdfdd,
  52         0xdfdf,
  53         0xffdf,
  54 };
  55 #endif
  56
  57 static void serial_setbrg_dev(struct s5p_uart *uart)
  58 {
  59         u32 uclk;
  60         u32 val;
  61
  62         // All UARTs share the same clock.
  63         uclk = clock_get_periph_rate(PERIPH_ID_UART3);
  64         val = uclk / get_uart_baudrate();
  65
  66         write32(&uart->ubrdiv, val / 16 - 1);
  67
  68         /*
  69          * FIXME(dhendrix): the original uart.h had a "br_rest" value which
  70          * does not seem relevant to the exynos5250... not entirely sure
  71          * where/if we need to worry about it here
  72          */
  73 #if 0
  74         if (s5p_uart_divslot())
  75                 writel(udivslot[val % 16], &uart->rest.slot);
  76         else
  77                 writeb(val % 16, &uart->rest.value);
  78 #endif
  79 }
  80
  81 /*
  82  * Initialise the serial port with the given baudrate. The settings
  83  * are always 8 data bits, no parity, 1 stop bit, no start bits.
  84  */
  85 static void exynos5_init_dev(struct s5p_uart *uart)
  86 {
  87         // TODO initialize with correct peripheral id by base_port.
  88         exynos_pinmux_uart3();
  89
  90         /* enable FIFOs */
  91         write32(&uart->ufcon, 0x1);
  92         write32(&uart->umcon, 0);
  93         /* 8N1 */
  94         write32(&uart->ulcon, 0x3);
  95         /* No interrupts, no DMA, pure polling */
  96         write32(&uart->ucon, 0x245);
  97
  98         serial_setbrg_dev(uart);
  99 }
 100
 101 static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 102 {
 103         unsigned int mask;
 104
 105         /*
 106          * UERSTAT
 107          * Break Detect [3]
 108          * Frame Err    [2] : receive operation
 109          * Parity Err   [1] : receive operation
 110          * Overrun Err  [0] : receive operation
 111          */
 112         if (op)
 113                 mask = 0x8;
 114         else
 115                 mask = 0xf;
 116
 117         return read32(&uart->uerstat) & mask;
 118 }
 119
 120 /*
 121  * Read a single byte from the serial port. Returns 1 on success, 0
 122  * otherwise. When the function is successful, the character read is
 123  * written into its argument c.
 124  */
 125 static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 126 {
 127         /* wait for character to arrive */
 128         while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
 129                                          RX_FIFO_FULL_MASK))) {
 130                 if (exynos5_uart_err_check(uart, 0))
 131                         return 0;
 132         }
 133
 134         return read8(&uart->urxh) & 0xff;
 135 }
 136
 137 /*
 138  * Output a single byte to the serial port.
 139  */
 140 static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data)
 141 {
 142         /* wait for room in the tx FIFO */
 143         while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 144                 if (exynos5_uart_err_check(uart, 1))
 145                         return;
 146         }
 147
 148         write8(&uart->utxh, data);
 149 }
 150
 151 static void exynos5_uart_tx_flush(struct s5p_uart *uart)
 152 {
 153         while (read32(&uart->ufstat) & 0x1ff0000);
 154 }
 155
 156 uintptr_t uart_platform_base(int idx)
 157 {
 158         if (idx < 4)
 159                 return 0x12c00000 + idx * 0x10000;
 160         else
 161                 return 0;
 162 }
 163
 164 void uart_init(int idx)
 165 {
 166         struct s5p_uart *uart = uart_platform_baseptr(idx);
 167         exynos5_init_dev(uart);
 168 }
 169
 170 unsigned char uart_rx_byte(int idx)
 171 {
 172         struct s5p_uart *uart = uart_platform_baseptr(idx);
 173         return exynos5_uart_rx_byte(uart);
 174 }
 175
 176 void uart_tx_byte(int idx, unsigned char data)
 177 {
 178         struct s5p_uart *uart = uart_platform_baseptr(idx);
 179         exynos5_uart_tx_byte(uart, data);
 180 }
 181
 182 void uart_tx_flush(int idx)
 183 {
 184         struct s5p_uart *uart = uart_platform_baseptr(idx);
 185         exynos5_uart_tx_flush(uart);
 186 }
 187
 188 #ifndef __PRE_RAM__
 189 void uart_fill_lb(void *data)
 190 {
 191         struct lb_serial serial;
 192         serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 193         serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 194         serial.baud = get_uart_baudrate();
 195         serial.regwidth = 4;
 196         lb_add_serial(&serial, data);
 197
 198         lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
 199 }
 200 #endif