mainboard/google/eve: Generate FPC device using SPI SSDT generator
[coreboot.git] / src / mainboard / google / eve / Kconfig
blob1a4a4c5b301cb4bf0f7d20b2f5d57bdd39419173
1 if BOARD_GOOGLE_EVE
3 config BOARD_SPECIFIC_OPTIONS
4         def_bool y
5         select BOARD_ID_AUTO
6         select BOARD_ROMSIZE_KB_16384
7         select DRIVERS_SPI_ACPI
8         select EC_GOOGLE_CHROMEEC
9         select EC_GOOGLE_CHROMEEC_LPC
10         select HAVE_ACPI_RESUME
11         select HAVE_ACPI_TABLES
12         select I2C_TPM
13         select MAINBOARD_HAS_CHROMEOS
14         select MAINBOARD_HAS_I2C_TPM_CR50
15         select MAINBOARD_HAS_TPM2
16         select MAINBOARD_USES_FSP2_0
17         select SOC_INTEL_SKYLAKE
18         select TPM2
20 config CHROMEOS
21         select EC_GOOGLE_CHROMEEC_SWITCHES
22         select HAS_RECOVERY_MRC_CACHE
23         select LID_SWITCH
24         select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
26 config DRIVERS_I2C_GENERIC
27         def_bool y
29 config DRIVERS_I2C_HID
30         def_bool y
32 config DRIVERS_I2C_WACOM
33         def_bool y
35 config DRIVERS_PS2_KEYBOARD
36         default y
38 config DRIVER_TPM_I2C_BUS
39         hex
40         default 0x1
42 config DRIVER_TPM_I2C_ADDR
43         hex
44         default 0x50
46 config DRIVER_TPM_I2C_IRQ
47         int
48         default 64  # GPE0_DW2_00 (GPP_E0)
50 config GBB_HWID
51         string
52         depends on CHROMEOS
53         default "EVE TEST 1394"
55 config IRQ_SLOT_COUNT
56         int
57         default 18
59 config MAINBOARD_DIR
60         string
61         default "google/eve"
63 config MAINBOARD_PART_NUMBER
64         string
65         default "Eve"
67 config MAINBOARD_FAMILY
68         string
69         default "Google_Eve"
71 config MAX_CPUS
72         int
73         default 8
75 endif