2 * This file is part of msrtool.
4 * Copyright (c) 2009 Marc Jones <marcj303@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 int k8_probe(const struct targetdef
*target
, const struct cpuid_t
*id
) {
19 return (VENDOR_AMD
== id
->vendor
) && (0xF == id
->family
);
23 * AMD BKDG Publication # 32559 Revision: 3.08 Issue Date: July 2007
25 const struct msrdef k8_msrs
[] = {
26 { 0xC0000080, MSRTYPE_RDWR
, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", {
29 { 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC
, {
30 { MSR1(0), "FXSAVE/FRSTOR disabled" },
31 { MSR1(1), "FXSAVE/FRSTOR enabled" },
34 { 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC
, {
35 { MSR1(0), "Long mode segment limit check disabled" },
36 { MSR1(1), "Long mode segment limit check enabled" },
39 { 12, 1, "SVME:", "SVM Enable", PRESENT_DEC
, {
40 { MSR1(0), "SVM features disabled" },
41 { MSR1(1), "SVM features enabled" },
44 { 11, 1, "NXE:", "No-Execute Page Enable", PRESENT_DEC
, {
45 { MSR1(0), "NXE features disabled" },
46 { MSR1(1), "NXE features enabled" },
49 { 10, 1, "LMA:", "Long Mode Active", PRESENT_DEC
, {
50 { MSR1(0), "Long Mode feature not active" },
51 { MSR1(1), "Long Mode feature active" },
55 { 8, 1, "LME:", "Long Mode Enable", PRESENT_DEC
, {
56 { MSR1(0), "Long Mode feature disabled" },
57 { MSR1(1), "Long Mode feature enabled" },
61 { 0, 1, "SYSCALL:", "System Call Extension Enable", PRESENT_DEC
, {
62 { MSR1(0), "System Call feature disabled" },
63 { MSR1(1), "System Call feature enabled" },
69 { 0xC0010010, MSRTYPE_RDWR
, MSR2(0, 0), "SYSCFG Register", "This register controls the system configuration", {
72 { 22, 1, "Tom2ForceMemTypeWB:", "Top of Memory 2 Memory Type Write Back", PRESENT_DEC
, {
73 { MSR1(0), "Tom2ForceMemTypeWB disabled" },
74 { MSR1(1), "Tom2ForceMemTypeWB enabled" },
77 { 21, 1, "MtrrTom2En:", "Top of Memory Address Register 2 Enable", PRESENT_DEC
, {
78 { MSR1(0), "MtrrTom2En disabled" },
79 { MSR1(1), "MtrrTom2En enabled" },
82 { 20, 1, "MtrrVarDramEn:", "Top of Memory Address Register and I/O Range Register Enable", PRESENT_DEC
, {
83 { MSR1(0), "MtrrVarDramEn disabled" },
84 { MSR1(1), "MtrrVarDramEn enabled" },
87 { 19, 1, "MtrrFixDramModEn:", "RdDram and WrDram Bits Modification Enable", PRESENT_DEC
, {
88 { MSR1(0), "MtrrFixDramModEn disabled" },
89 { MSR1(1), "MtrrFixDramModEn enabled" },
92 { 18, 1, "MtrrFixDramEn:", "Fixed RdDram and WrDram Attributes Enable", PRESENT_DEC
, {
93 { MSR1(0), "MtrrFixDramEn disabled" },
94 { MSR1(1), "MtrrFixDramEn enabled" },
97 { 17, 1, "SysUcLockEn:", "System Interface Lock Command Enable", PRESENT_DEC
, {
98 { MSR1(0), "SysUcLockEn disabled" },
99 { MSR1(1), "SysUcLockEn enabled" },
102 { 16, 1, "ChxToDirtyDis:", "Change to Dirty Command Disable", PRESENT_DEC
, {
103 { MSR1(0), "ChxToDirtyDis disabled" },
104 { MSR1(1), "ChxToDirtyDis enabled" },
108 { 10, 1, "SetDirtyEnO:", "SharedToDirty Command for O->M State Transition Enable", PRESENT_DEC
, {
109 { MSR1(0), "SetDirtyEnO disabled" },
110 { MSR1(1), "SetDirtyEnO enabled" },
113 { 9, 1, "SetDirtyEnS:", "SharedToDirty Command for S->M State Transition Enable", PRESENT_DEC
, {
114 { MSR1(0), "SetDirtyEnS disabled" },
115 { MSR1(1), "SetDirtyEnS enabled" },
118 { 8, 1, "SetDirtyEnE:", "CleanToDirty Command for E->M State Transition Enable", PRESENT_DEC
, {
119 { MSR1(0), "SetDirtyEnE disabled" },
120 { MSR1(1), "SetDirtyEnE enabled" },
123 { 7, 3, "SysVicLimit:", "Outstanding Victim Bus Command Limit", PRESENT_HEX
, {
126 { 4, 5, "SysAckLimit:", "Outstanding Bus Command Limit", PRESENT_HEX
, {
132 { 0xC0010015, MSRTYPE_RDWR
, MSR2(0, 0), "HWCR Register", "This register controls the hardware configuration", {
133 { 63, 32, RESERVED
},
135 { 29, 6, "START_FID:", "Status of the startup FID", PRESENT_HEX
, {
139 { 18, 1, "MCi_STATUS_WREN:", "MCi Status Write Enable", PRESENT_DEC
, {
140 { MSR1(0), "MCi_STATUS_WREN disabled" },
141 { MSR1(1), "MCi_STATUS_WREN enabled" },
144 { 17, 1, "WRAP32DIS:", "32-bit Address Wrap Disable", PRESENT_DEC
, {
145 { MSR1(0), "WRAP32DIS clear" },
146 { MSR1(1), "WRAP32DIS set" },
150 { 15, 1, "SSEDIS:", "SSE Instructions Disable", PRESENT_DEC
, {
151 { MSR1(0), "SSEDIS clear" },
152 { MSR1(1), "SSEDIS set" },
155 { 14, 1, "RSMSPCYCDIS:", "Special Bus Cycle On RSM Disable", PRESENT_DEC
, {
156 { MSR1(0), "RSMSPCYCDIS clear" },
157 { MSR1(1), "RSMSPCYCDIS set" },
160 { 13, 1, "SMISPCYCDIS:", "Special Bus Cycle On SMI Disable", PRESENT_DEC
, {
161 { MSR1(0), "SMISPCYCDIS clear" },
162 { MSR1(1), "SMISPCYCDIS set" },
165 { 12, 1, "HLTXSPCYCEN:", "Enable Special Bus Cycle On Exit From HLT", PRESENT_DEC
, {
166 { MSR1(0), "HLTXSPCYCEN disabled" },
167 { MSR1(1), "HLTXSPCYCEN enabled" },
171 { 8, 1, "IGNNE_EM:", "IGNNE Port Emulation Enable", PRESENT_DEC
, {
172 { MSR1(0), "IGNNE_EM disabled" },
173 { MSR1(1), "IGNNE_EM enabled" },
176 { 7, 1, "DISLOCK:", "Disable x86 LOCK prefix functionality", PRESENT_DEC
, {
177 { MSR1(0), "DISLOCK clear" },
178 { MSR1(1), "DISLOCK set" },
181 { 6, 1, "FFDIS:", "TLB Flush Filter Disable", PRESENT_DEC
, {
182 { MSR1(0), "FFDIS clear" },
183 { MSR1(1), "FFDIS set" },
187 { 4, 1, "INVD_WBINVD:", "INVD to WBINVD Conversion", PRESENT_DEC
, {
188 { MSR1(0), "INVD_WBINVD disabled" },
189 { MSR1(1), "INVD_WBINVD enabled" },
192 { 3, 1, "TLBCACHEDIS:", "TLB Cacheable Memory Disable", PRESENT_DEC
, {
193 { MSR1(0), "TLBCACHEDIS clear" },
194 { MSR1(1), "TLBCACHEDIS set" },
198 { 1, 1, "SLOWFENCE:", "Slow SFENCE Enable", PRESENT_DEC
, {
199 { MSR1(0), "SLOWFENCE disabled" },
200 { MSR1(1), "SLOWFENCE enabled" },
203 { 0, 1, "SMMLOCK:", "SMM Configuration Lock", PRESENT_DEC
, {
204 { MSR1(0), "SMMLOCK disabled" },
205 { MSR1(1), "SMMLOCK enabled" },
211 { 0xC001001F, MSRTYPE_RDWR
, MSR2(0, 0), "NB_CFG Register", "", {
213 { 54, 1, "InitApicIdCpuIdLo:", "CpuId and NodeId[2:0] bit field positions are swapped in the APICID", PRESENT_DEC
, {
214 { MSR1(0), "CpuId and NodeId not swapped" },
215 { MSR1(1), "CpuId and NodeId swapped" },
219 { 45, 1, "DisUsSysMgtRqToNLdt:", "Disable Upstream System Management Rebroadcast", PRESENT_DEC
, {
220 { MSR1(0), "Upstream Rebroadcast disabled" },
221 { MSR1(1), "Upstream Rebroadcast enabled" },
225 { 43, 1, "DisThmlPfMonSmiInt:", "Disable Performance Monitor SMI", PRESENT_DEC
, {
226 { MSR1(0), "Performance Monitor SMI enabled" },
227 { MSR1(1), "Performance Monitor SMI disabled" },
231 { 36, 1, "DisDatMsk:", "Disables DRAM data masking function", PRESENT_DEC
, {
232 { MSR1(0), "DRAM data masking enabled" },
233 { MSR1(1), "DRAM data masking disabled" },
237 { 31, 1, "DisCohLdtCfg:", "Disable Coherent HyperTransport Configuration Accesses", PRESENT_DEC
, {
238 { MSR1(0), "Coherent HyperTransport Configuration enabled" },
239 { MSR1(1), "Coherent HyperTransport Configuration disabled" },
242 { 30, 21, RESERVED
},
243 { 9, 1, "DisRefUseFreeBuf:", "Disable Display Refresh from Using Free List Buffers", PRESENT_DEC
, {
244 { MSR1(0), "Display refresh requests enabled" },
245 { MSR1(1), "Display refresh requests disabled" },
251 { 0xC001001A, MSRTYPE_RDWR
, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", {
252 { 63, 24, RESERVED
},
253 { 39, 8, "TOM 39-32", "", PRESENT_HEX
, {
256 { 31, 9, "TOM 31-23", "", PRESENT_HEX
, {
259 { 22, 23, RESERVED
},
263 { 0xC001001D, MSRTYPE_RDWR
, MSR2(0, 0), "TOP_MEM2 Register", "This register indicates the Top of Memory above 4GB", {
264 { 63, 24, RESERVED
},
265 { 39, 8, "TOM2 39-32", "", PRESENT_HEX
, {
268 { 31, 9, "TOM2 31-23", "", PRESENT_HEX
, {
271 { 22, 23, RESERVED
},
275 { 0xC0010016, MSRTYPE_RDWR
, MSR2(0, 0), "IORRBase0", "This register holds the base of the variable I/O range", {
276 { 63, 24, RESERVED
},
277 { 39, 8, "BASE 27-20", "", PRESENT_HEX
, {
280 { 31, 20, "BASE 20-0", "", PRESENT_HEX
, {
284 { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC
, {
285 { MSR1(0), "RdDram disabled" },
286 { MSR1(1), "RdDram enabled" },
289 { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC
, {
290 { MSR1(0), "WrDram disabled" },
291 { MSR1(1), "WrDram enabled" },
297 { 0xC0010017, MSRTYPE_RDWR
, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", {
298 { 63, 24, RESERVED
},
299 { 39, 8, "MASK 27-20", "", PRESENT_HEX
, {
302 { 31, 20, "MASK 20-0", "", PRESENT_HEX
, {
305 { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC
, {
306 { MSR1(0), "V I/O range disabled" },
307 { MSR1(1), "V I/O range enabled" },
310 { 10, 11, RESERVED
},
314 { 0xC0010018, MSRTYPE_RDWR
, MSR2(0, 0), "IORRBase1", "This register holds the base of the variable I/O range", {
315 { 63, 24, RESERVED
},
316 { 39, 8, "BASE 27-20", "", PRESENT_HEX
, {
319 { 31, 20, "BASE 20-0", "", PRESENT_HEX
, {
323 { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC
, {
324 { MSR1(0), "RdDram disabled" },
325 { MSR1(1), "RdDram enabled" },
328 { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC
, {
329 { MSR1(0), "WrDram disabled" },
330 { MSR1(1), "WrDram enabled" },
336 { 0xC0010019, MSRTYPE_RDWR
, MSR2(0, 0), "IORRMask1", "This register holds the mask of the variable I/O range", {
337 { 63, 24, RESERVED
},
338 { 39, 8, "MASK 27-20", "", PRESENT_HEX
, {
341 { 31, 20, "MASK 20-0", "", PRESENT_HEX
, {
344 { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC
, {
345 { MSR1(0), "V I/O range disabled" },
346 { MSR1(1), "V I/O range enabled" },
349 { 10, 11, RESERVED
},