soc/intel/common/block: Add Intel common PMC controller support for KBL, APL
[coreboot.git] / src / include / gpio.h
blob31602425624616604dae0fb89f4d776d50e43f56
1 /*
2 * This file is part of the coreboot project.
4 * Copyright 2014 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef __SRC_INCLUDE_GPIO_H__
17 #define __SRC_INCLUDE_GPIO_H__
19 #include <soc/gpio.h>
20 #include <types.h>
22 /* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */
23 _Static_assert(sizeof(gpio_t) <= sizeof(u32), "gpio_t doesn't fit in lb_gpio");
25 /* The following functions must be implemented by SoC/board code. */
26 int gpio_get(gpio_t gpio);
27 void gpio_set(gpio_t gpio, int value);
28 void gpio_input_pulldown(gpio_t gpio);
29 void gpio_input_pullup(gpio_t gpio);
30 void gpio_input(gpio_t gpio);
31 void gpio_output(gpio_t gpio, int value);
32 int _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first);
35 * This function may be implemented by SoC/board code to provide
36 * a mapping from a GPIO pin to controller by returning the ACPI
37 * path for the controller that owns this GPIO.
39 * If not implemented the default handler will return NULL.
41 const char *gpio_acpi_path(gpio_t gpio);
44 * This function may be implemented by SoC/board code to provide
45 * a mapping from the internal representation of a GPIO to the 16bit
46 * value used in an ACPI GPIO pin table entry.
48 * If not implemented by the SOC the default handler will return 0
49 * because the underlying type of gpio_t is unknown.
51 uint16_t gpio_acpi_pin(gpio_t gpio);
54 * Read the value presented by the set of GPIOs, when each pin is interpreted
55 * as a base-2 digit (LOW = 0, HIGH = 1).
57 * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
58 * num_gpio: number of pins to read.
60 * There are also pulldown and pullup variants which default each gpio to
61 * be configured with an internal pulldown and pullup, respectively.
63 int gpio_base2_value(const gpio_t gpio[], int num_gpio);
64 int gpio_pulldown_base2_value(const gpio_t gpio[], int num_gpio);
65 int gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio);
68 * Read the value presented by the set of GPIOs, when each pin is interpreted
69 * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2).
70 * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5
71 * BASE3() from <base3.h> can generate numbers to compare the result to.
73 * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
74 * num_gpio: number of pins to read.
76 static inline int gpio_base3_value(const gpio_t gpio[], int num_gpio)
78 return _gpio_base3_value(gpio, num_gpio, 0);
82 * Read the value presented by the set of GPIOs, when each pin is interpreted
83 * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2) in a non-standard
84 * ternary number system where the first 2^n natural numbers are represented
85 * as they would be in a binary system (without any Z digits), and the following
86 * 3^n-2^n numbers use the remaining ternary representations in the normal
87 * ternary system order (skipping the values that were already used up).
88 * This is useful for boards which initially used a binary board ID and later
89 * decided to switch to tri-state after some revisions have already been built.
90 * Example: For num_gpio = 2 we get the following representation:
92 * Number X1 X0
93 * 0 0 0
94 * 1 0 1
95 * 2 1 0
96 * 3 1 1 // Start counting ternaries back at 0 after this
97 * 4 0 2 // Skipping 00 and 01 which are already used up
98 * 5 1 2 // Skipping 10 and 11 which are already used up
99 * 6 2 0
100 * 7 2 1
101 * 8 2 2
103 * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
104 * num_gpio: number of pins to read.
106 static inline int gpio_binary_first_base3_value(const gpio_t gpio[],
107 int num_gpio)
109 return _gpio_base3_value(gpio, num_gpio, 1);
112 #endif /* __SRC_INCLUDE_GPIO_H__ */