src/device/pcix_device.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Linux Networx
   5  * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <device/pci_ids.h>
  21 #include <device/pcix.h>
  22
  23 static void pcix_tune_dev(device_t dev)
  24 {
  25         u32 status;
  26         u16 orig_cmd, cmd;
  27         unsigned int cap, max_read, max_tran;
  28
  29         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
  30                 return;
  31
  32         cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  33         if (!cap)
  34                 return;
  35
  36         printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev));
  37
  38         status = pci_read_config32(dev, cap + PCI_X_STATUS);
  39         orig_cmd = cmd = pci_read_config16(dev, cap + PCI_X_CMD);
  40
  41         max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
  42         max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
  43         if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
  44                 cmd &= ~PCI_X_CMD_MAX_READ;
  45                 cmd |= max_read << 2;
  46         }
  47         if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
  48                 cmd &= ~PCI_X_CMD_MAX_SPLIT;
  49                 cmd |= max_tran << 4;
  50         }
  51
  52         /* Don't attempt to handle PCI-X errors. */
  53         cmd &= ~PCI_X_CMD_DPERR_E;
  54
  55         /* Enable relaxed ordering. */
  56         cmd |= PCI_X_CMD_ERO;
  57
  58         if (orig_cmd != cmd)
  59                 pci_write_config16(dev, cap + PCI_X_CMD, cmd);
  60 }
  61
  62 static void pcix_tune_bus(struct bus *bus)
  63 {
  64         device_t child;
  65
  66         for (child = bus->children; child; child = child->sibling)
  67                 pcix_tune_dev(child);
  68 }
  69
  70 const char *pcix_speed(u16 sstatus)
  71 {
  72         static const char conventional[] = "Conventional PCI";
  73         static const char pcix_66mhz[] = "66MHz PCI-X";
  74         static const char pcix_100mhz[] = "100MHz PCI-X";
  75         static const char pcix_133mhz[] = "133MHz PCI-X";
  76         static const char pcix_266mhz[] = "266MHz PCI-X";
  77         static const char pcix_533mhz[] = "533MHZ PCI-X";
  78         static const char unknown[] = "Unknown";
  79         const char *result;
  80
  81         result = unknown;
  82
  83         switch (PCI_X_SSTATUS_MFREQ(sstatus)) {
  84         case PCI_X_SSTATUS_CONVENTIONAL_PCI:
  85                 result = conventional;
  86                 break;
  87         case PCI_X_SSTATUS_MODE1_66MHZ:
  88                 result = pcix_66mhz;
  89                 break;
  90         case PCI_X_SSTATUS_MODE1_100MHZ:
  91                 result = pcix_100mhz;
  92                 break;
  93         case PCI_X_SSTATUS_MODE1_133MHZ:
  94                 result = pcix_133mhz;
  95                 break;
  96         case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
  97         case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
  98         case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
  99                 result = pcix_266mhz;
 100                 break;
 101         case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
 102         case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
 103         case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
 104                 result = pcix_533mhz;
 105                 break;
 106         }
 107
 108         return result;
 109 }
 110
 111 void pcix_scan_bridge(device_t dev)
 112 {
 113         unsigned int pos;
 114         u16 sstatus;
 115
 116         do_pci_scan_bridge(dev, pci_scan_bus);
 117
 118         /* Find the PCI-X capability. */
 119         pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 120         sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
 121
 122         if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
 123                 pcix_tune_bus(dev->link_list);
 124
 125         /* Print the PCI-X bus speed. */
 126         printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary,
 127                pcix_speed(sstatus));
 128 }
 129
 130 /** Default device operations for PCI-X bridges */
 131 static struct pci_operations pcix_bus_ops_pci = {
 132         .set_subsystem = 0,
 133 };
 134
 135 struct device_operations default_pcix_ops_bus = {
 136         .read_resources   = pci_bus_read_resources,
 137         .set_resources    = pci_dev_set_resources,
 138         .enable_resources = pci_bus_enable_resources,
 139         .init             = 0,
 140         .scan_bus         = pcix_scan_bridge,
 141         .enable           = 0,
 142         .reset_bus        = pci_bus_reset,
 143         .ops_pci          = &pcix_bus_ops_pci,
 144 };