util/bincfg/ifd-x200.set

   1 #
   2 # Copyright (C) 2017 Damien Zammit <damien@zamaudio.com>
   3 #
   4 # This program is free software: you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License as published by
   6 # the Free Software Foundation, either version 3 of the License, or
   7 # (at your option) any later version.
   8 #
   9 # This program is distributed in the hope that it will be useful,
  10 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 # GNU General Public License for more details.
  13 #
  14 #
  15 # X200 Liberated Flash Descriptor
  16 # Layout:
  17 #       0x0000 - 0x1000  : IFD
  18 #       0x1000 - 0x3000  : GbE x2
  19 #       0x3000 - ROMSIZE : BIOS
  20 {
  21         "fd_signature" = 0xff0a55a,
  22
  23         "flmap0_fcba" = 0x1,
  24         "flmap0_nc" = 0x0,
  25         "flmap0_reserved0" = 0x0,
  26         "flmap0_frba" = 0x4,
  27         "flmap0_nr" = 0x3,
  28         "flmap0_reserved1" = 0x0,
  29         "flmap1_fmba" = 0x6,
  30         "flmap1_nm" = 0x2,
  31         "flmap1_reserved" = 0x0,
  32         "flmap1_fisba" = 0x10,
  33         "flmap1_isl" = 0x2,
  34         "flmap2_fmsba" = 0x20,
  35         "flmap2_msl" = 0x1,
  36         "flmap2_reserved" = 0x0,
  37
  38         "flcomp_density1" = 0x4,
  39         "flcomp_density2" = 0x2,
  40         "flcomp_reserved0" = 0x0,
  41         "flcomp_reserved1" = 0x0,
  42         "flcomp_reserved2" = 0x0,
  43         "flcomp_readclockfreq" = 0x0,
  44         "flcomp_fastreadsupp" = 0x1,
  45         "flcomp_fastreadfreq" = 0x1,
  46         "flcomp_w_eraseclkfreq" = 0x0,
  47         "flcomp_r_statclkfreq" = 0x0,
  48         "flcomp_reserved3" = 0x0,
  49         "flill" = 0x0,
  50         "flbp" = 0x0,
  51         "comp_padding"[0x24] = 0xff,
  52
  53         "flreg0_base" = 0x0,
  54         "flreg0_reserved0" = 0x0,
  55         "flreg0_limit" = 0x0,
  56         "flreg0_reserved1" = 0x0,
  57         "flreg1_base" = 0x3,
  58         "flreg1_reserved0" = 0x0,
  59         "flreg1_limit" = 0x7ff,
  60         "flreg1_reserved1" = 0x0,
  61         "flreg2_base" = 0x1fff,
  62         "flreg2_reserved0" = 0x0,
  63         "flreg2_limit" = 0x0,
  64         "flreg2_reserved1" = 0x0,
  65         "flreg3_base" = 0x1,
  66         "flreg3_reserved0" = 0x0,
  67         "flreg3_limit" = 0x2,
  68         "flreg3_reserved1" = 0x0,
  69         "flreg4_base" = 0x1fff,
  70         "flreg4_reserved0" = 0x0,
  71         "flreg4_limit" = 0x0,
  72         "flreg4_reserved1" = 0x0,
  73         "flreg_padding"[12] = 0xff,
  74
  75         "flmstr1_requesterid" = 0x0,
  76         "flmstr1_r_fd" = 0x1,
  77         "flmstr1_r_bios" = 0x1,
  78         "flmstr1_r_me" = 0x1,
  79         "flmstr1_r_gbe" = 0x1,
  80         "flmstr1_r_pd" = 0x1,
  81         "flmstr1_r_reserved" = 0x0,
  82         "flmstr1_w_fd" = 0x1,
  83         "flmstr1_w_bios" = 0x1,
  84         "flmstr1_w_me" = 0x1,
  85         "flmstr1_w_gbe" = 0x1,
  86         "flmstr1_w_pd" = 0x1,
  87         "flmstr1_w_reserved" = 0x0,
  88         "flmstr2_requesterid" = 0x0,
  89         "flmstr2_r_fd" = 0x0,
  90         "flmstr2_r_bios" = 0x0,
  91         "flmstr2_r_me" = 0x0,
  92         "flmstr2_r_gbe" = 0x0,
  93         "flmstr2_r_pd" = 0x0,
  94         "flmstr2_r_reserved" = 0x0,
  95         "flmstr2_w_fd" = 0x0,
  96         "flmstr2_w_bios" = 0x0,
  97         "flmstr2_w_me" = 0x0,
  98         "flmstr2_w_gbe" = 0x0,
  99         "flmstr2_w_pd" = 0x0,
 100         "flmstr2_w_reserved" = 0x0,
 101         "flmstr3_requesterid" = 0x218,
 102         "flmstr3_r_fd" = 0x0,
 103         "flmstr3_r_bios" = 0x0,
 104         "flmstr3_r_me" = 0x0,
 105         "flmstr3_r_gbe" = 0x1,
 106         "flmstr3_r_pd" = 0x0,
 107         "flmstr3_r_reserved" = 0x0,
 108         "flmstr3_w_fd" = 0x0,
 109         "flmstr3_w_bios" = 0x0,
 110         "flmstr3_w_me" = 0x0,
 111         "flmstr3_w_gbe" = 0x1,
 112         "flmstr3_w_pd" = 0x0,
 113         "flmstr3_w_reserved" = 0x0,
 114         "flmstr_padding"[0x94] = 0xff,
 115
 116         "ich0_medisable" = 0x1,
 117         "ich0_reserved0" = 0x4,
 118         "ich0_tcomode" = 0x1,
 119         "ich0_mesmbusaddr" = 0x64,
 120         "ich0_bmcmode" = 0x0,
 121         "ich0_trippointsel" = 0x0,
 122         "ich0_reserved1" = 0x0,
 123         "ich0_integratedgbe" = 0x1,
 124         "ich0_lanphy" = 0x1,
 125         "ich0_reserved2" = 0x0,
 126         "ich0_dmireqiddisable" = 0x0,
 127         "ich0_me2smbusaddr" = 0x0,
 128         "ich1_dynclk_nmlink" = 0x1,
 129         "ich1_dynclk_smlink" = 0x1,
 130         "ich1_dynclk_mesmbus" = 0x1,
 131         "ich1_dynclk_sst" = 0x1,
 132         "ich1_reserved0" = 0x0,
 133         "ich1_nmlink_npostreqs" = 0x1,
 134         "ich1_reserved1" = 0x0,
 135         "ich1_reserved2" = 0x0,
 136         "ichstrap_padding"[0xf8] = 0xff,
 137         "mch0_medisable" = 0x1,
 138         "mch0_mebootfromflash" = 0x0,
 139         "mch0_tpmdisable" = 0x1,
 140         "mch0_reserved0" = 0x7,
 141         "mch0_spifingerprinton" = 0x1,
 142         "mch0_mealtdisable" = 0x0,
 143         "mch0_reserved1" = 0xff,
 144         "mch0_reserved2" = 0xffff,
 145         "mchstrap_padding"[0xcdc] = 0xff,
 146
 147         "mevscc_jid0" = 0x1720c2,
 148         "mevscc_vscc0" = 0x20052005,
 149         "mevscc_jid1" = 0x1730ef,
 150         "mevscc_vscc1" = 0x20052005,
 151         "mevscc_jid2" = 0x481f,
 152         "mevscc_vscc2" = 0x20152015,
 153         "mevscc_padding"[4] = 0xff,
 154         "mevscc_tablebase" = 0xee,
 155         "mevscc_tablelength" = 0x6,
 156         "mevscc_reserved" = 0x0,
 157
 158         "oem_magic0" = 0x4c,
 159         "oem_magic1" = 0x49,
 160         "oem_magic2" = 0x42,
 161         "oem_magic3" = 0x45,
 162         "oem_magic4" = 0x52,
 163         "oem_magic5" = 0x41,
 164         "oem_magic6" = 0x54,
 165         "oem_magic7" = 0x45,
 166         "oem_padding"[0xf8] = 0xff
 167 }