Documentation: Fix sphinx configuration
[coreboot.git] / src / include / memory_info.h
blobf4a200995c893b7d595b2f6156145236a9019ca6
1 /* Memory information */
2 /* SPDX-License-Identifier: GPL-2.0-only */
4 #ifndef _MEMORY_INFO_H_
5 #define _MEMORY_INFO_H_
7 #include <stdint.h>
8 #include <stdbool.h>
10 #define DIMM_INFO_SERIAL_SIZE 4
11 #define DIMM_INFO_PART_NUMBER_SIZE 33
12 #define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */
14 /**
15 * If this table is filled and put in CBMEM,
16 * then these info in CBMEM will be used to generate smbios type 17 table
18 * Values are specified according to the JEDEC SPD Standard.
20 struct dimm_info {
22 * Size of the module in MiB.
24 uint32_t dimm_size;
26 * SMBIOS (not SPD) device type.
28 * See the smbios.h smbios_memory_type enum.
30 uint16_t ddr_type;
31 uint16_t ddr_frequency;
32 uint8_t rank_per_dimm;
33 uint8_t channel_num;
34 uint8_t dimm_num;
35 uint8_t bank_locator;
37 * SPD serial number.
39 uint8_t serial[DIMM_INFO_SERIAL_SIZE];
41 * The last byte is '\0' for the end of string
43 * Must contain only printable ASCII.
45 uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
47 * SPD Manufacturer ID
49 uint16_t mod_id;
51 * SPD Module Type.
53 * See spd.h for valid values.
55 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
57 uint8_t mod_type;
59 * SPD bus width.
61 * Bits 0 - 2 encode the primary bus width:
62 * 0b000 = 8 bit width
63 * 0b001 = 16 bit width
64 * 0b010 = 32 bit width
65 * 0b011 = 64 bit width
67 * Bits 3 - 4 encode the extension bits (ECC):
68 * 0b00 = 0 extension bits
69 * 0b01 = 8 bit of ECC
71 * e.g.,
72 * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
73 * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
75 * See the smbios.h smbios_memory_bus_width enum.
77 uint8_t bus_width;
79 * Voltage Level
81 uint16_t vdd_voltage;
82 } __packed;
84 struct memory_info {
85 /* controller specific */
86 bool ecc_capable;
87 /* Maximum capacity the DRAM controller/mainboard supports */
88 uint32_t max_capacity_mib;
89 /* Maximum number of DIMMs the DRAM controller/mainboard supports */
90 uint16_t number_of_devices;
92 /* active DIMM configuration */
93 uint8_t dimm_cnt;
94 struct dimm_info dimm[DIMM_INFO_TOTAL];
95 } __packed;
97 #endif