2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
39 prompt "Compiler to use"
42 This option allows you to select the compiler used for building
44 You must build the coreboot crosscompiler for the board that you
47 To build all the GCC crosscompilers (takes a LONG time), run:
50 For help on individual architectures, run the command:
56 Use the GNU Compiler Collection (GCC) to build coreboot.
58 For details see http://gcc.gnu.org.
60 config COMPILER_LLVM_CLANG
61 bool "LLVM/clang (TESTING ONLY - Not currently working)"
63 Use LLVM/clang to build coreboot. To use this, you must build the
64 coreboot version of the clang compiler. Run the command
66 Note that this option is not currently working correctly and should
67 really only be selected if you're trying to work on getting clang
70 For details see http://clang.llvm.org.
75 bool "Allow building with any toolchain"
77 depends on COMPILER_GCC
79 Many toolchains break when building coreboot since it uses quite
80 unusual linker features. Unless developers explicitely request it,
81 we'll have to assume that they use their distro compiler by mistake.
82 Make sure that using patched compilers is a conscious decision.
85 bool "Use ccache to speed up (re)compilation"
88 Enables the use of ccache for faster builds.
90 Requires the ccache utility in your system $PATH.
92 For details see https://ccache.samba.org.
95 bool "Generate flashmap descriptor parser using flex and bison"
98 Enable this option if you are working on the flashmap descriptor
99 parser and made changes to fmd_scanner.l or fmd_parser.y.
101 Otherwise, say N to use the provided pregenerated scanner/parser.
103 config SCONFIG_GENPARSER
104 bool "Generate SCONFIG parser using flex and bison"
107 Enable this option if you are working on the sconfig device tree
108 parser and made changes to sconfig.l or sconfig.y.
110 Otherwise, say N to use the provided pregenerated scanner/parser.
112 config USE_OPTION_TABLE
113 bool "Use CMOS for configuration values"
115 depends on HAVE_OPTION_TABLE
117 Enable this option if coreboot shall read options from the "CMOS"
118 NVRAM instead of using hard-coded values.
120 config STATIC_OPTION_TABLE
121 bool "Load default configuration values into CMOS on each boot"
123 depends on USE_OPTION_TABLE
125 Enable this option to reset "CMOS" NVRAM values to default on
126 every boot. Use this if you want the NVRAM configuration to
127 never be modified from its default values.
129 config UNCOMPRESSED_RAMSTAGE
133 config COMPRESS_RAMSTAGE
134 bool "Compress ramstage with LZMA"
135 default y if !UNCOMPRESSED_RAMSTAGE
138 Compress ramstage to save memory in the flash image. Note
139 that decompression might slow down booting if the boot flash
140 is connected through a slow link (i.e. SPI).
142 config COMPRESS_PRERAM_STAGES
143 bool "Compress romstage and verstage with LZ4"
147 Compress romstage and (if it exists) verstage with LZ4 to save flash
148 space and speed up boot, since the time for reading the image from SPI
149 (and in the vboot case verifying it) is usually much greater than the
150 time spent decompressing. Doesn't work for XIP stages (assume all
151 ARCH_X86 for now) for obvious reasons.
153 config INCLUDE_CONFIG_FILE
154 bool "Include the coreboot .config file into the ROM image"
157 Include the .config file that was used to compile coreboot
158 in the (CBFS) ROM image. This is useful if you want to know which
159 options were used to build a specific coreboot.rom image.
161 Saying Y here will increase the image size by 2-3KB.
163 You can use the following command to easily list the options:
165 grep -a CONFIG_ coreboot.rom
167 Alternatively, you can also use cbfstool to print the image
168 contents (including the raw 'config' item we're looking for).
172 $ cbfstool coreboot.rom print
173 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
177 Name Offset Type Size
178 cmos_layout.bin 0x0 cmos layout 1159
179 fallback/romstage 0x4c0 stage 339756
180 fallback/ramstage 0x53440 stage 186664
181 fallback/payload 0x80dc0 payload 51526
182 config 0x8d740 raw 3324
183 (empty) 0x8e480 null 3610440
185 config NO_XIP_EARLY_STAGES
187 default n if ARCH_X86
190 Identify if early stages are eXecute-In-Place(XIP).
192 config EARLY_CBMEM_INIT
193 def_bool !LATE_CBMEM_INIT
195 config EARLY_CBMEM_LIST
199 Enable display of CBMEM during romstage and postcar.
201 config COLLECT_TIMESTAMPS
202 bool "Create a table of timestamps collected during boot"
205 Make coreboot create a table of timer-ID/timer-value pairs to
206 allow measuring time spent at different phases of the boot process.
209 bool "Allow use of binary-only repository"
212 This draws in the blobs repository, which contains binary files that
213 might be required for some chipsets or boards.
214 This flag ensures that a "Free" option remains available for users.
217 bool "Code coverage support"
218 depends on COMPILER_GCC
221 Add code coverage support for coreboot. This will store code
222 coverage information in CBMEM for extraction from user space.
225 config RELOCATABLE_MODULES
229 If RELOCATABLE_MODULES is selected then support is enabled for
230 building relocatable modules in the RAM stage. Those modules can be
231 loaded anywhere and all the relocations are handled automatically.
233 config RELOCATABLE_RAMSTAGE
234 depends on EARLY_CBMEM_INIT
235 bool "Build the ramstage to be relocatable in 32-bit address space."
237 select RELOCATABLE_MODULES
239 The reloctable ramstage support allows for the ramstage to be built
240 as a relocatable module. The stage loader can identify a place
241 out of the OS way so that copying memory is unnecessary during an S3
242 wake. When selecting this option the romstage is responsible for
243 determing a stack location to use for loading the ramstage.
245 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
246 depends on RELOCATABLE_RAMSTAGE
247 bool "Cache the relocated ramstage outside of cbmem."
250 The relocated ramstage is saved in an area specified by the
251 by the board and/or chipset.
253 config NO_STAGE_CACHE
257 Do not save any component in stage cache for resume path. On resume,
258 all components would be read back from CBFS again.
260 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
262 prompt "Bootblock behaviour"
263 default BOOTBLOCK_SIMPLE
265 config BOOTBLOCK_SIMPLE
266 bool "Always load fallback"
268 config BOOTBLOCK_NORMAL
269 bool "Switch to normal if CMOS says so"
273 # To be selected by arch, SoC or mainboard if it does not want use the normal
274 # src/lib/bootblock.c#main() C entry point.
275 config BOOTBLOCK_CUSTOM
279 config BOOTBLOCK_SOURCE
281 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
282 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
284 # To be selected by arch or platform if a C environment is available during the
285 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
286 config C_ENVIRONMENT_BOOTBLOCK
290 config SKIP_MAX_REBOOT_CNT_CLEAR
291 bool "Do not clear reboot count after successful boot"
293 depends on BOOTBLOCK_NORMAL
295 Do not clear the reboot count immediately after successful boot.
296 Set to allow the payload to control normal/fallback image recovery.
297 Note that it is the responsibility of the payload to reset the
298 normal boot bit to 1 after each successsful boot.
301 bool "Update existing coreboot.rom image"
304 If this option is enabled, no new coreboot.rom file
305 is created. Instead it is expected that there already
306 is a suitable file for further processing.
307 The bootblock will not be modified.
309 If unsure, select 'N'
311 config GENERIC_GPIO_LIB
315 If enabled, compile the generic GPIO library. A "generic" GPIO
316 implies configurability usually found on SoCs, particularly the
317 ability to control internal pull resistors.
323 Mainboards that can read a board ID from the hardware straps
324 (ie. GPIO) select this configuration option.
326 config BOARD_ID_MANUAL
329 depends on !BOARD_ID_AUTO
331 If you want to maintain a board ID, but the hardware does not
332 have straps to automatically determine the ID, you can say Y
333 here and add a file named 'board_id' to CBFS. If you don't know
334 what this is about, say N.
336 config BOARD_ID_STRING
339 depends on BOARD_ID_MANUAL
341 This string is placed in the 'board_id' CBFS file for indicating
344 config RAM_CODE_SUPPORT
348 If enabled, coreboot discovers RAM configuration (value obtained by
349 reading board straps) and stores it in coreboot table.
351 config BOOTSPLASH_IMAGE
352 bool "Add a bootsplash image"
354 Select this option if you have a bootsplash image that you would
355 like to add to your ROM.
357 This will only add the image to the ROM. To actually run it check
358 options under 'Display' section.
360 config BOOTSPLASH_FILE
361 string "Bootsplash path and filename"
362 depends on BOOTSPLASH_IMAGE
363 default "bootsplash.jpg"
365 The path and filename of the file to use as graphical bootsplash
366 screen. The file format has to be jpg.
372 source "src/mainboard/Kconfig"
376 default "devicetree.cb"
378 This symbol allows mainboards to select a different file under their
379 mainboard directory for the devicetree.cb file. This allows the board
380 variants that need different devicetrees to be in the same directory.
382 Examples: "devicetree.variant.cb"
383 "variant/devicetree.cb"
385 # defaults for CBFS_SIZE are set at the end of the file.
387 hex "Size of CBFS filesystem in ROM"
389 This is the part of the ROM actually managed by CBFS, located at the
390 end of the ROM (passed through cbfstool -o) on x86 and at at the start
391 of the ROM (passed through cbfstool -s) everywhere else. It defaults
392 to span the whole ROM on all but Intel systems that use an Intel Firmware
393 Descriptor. It can be overridden to make coreboot live alongside other
394 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
398 string "fmap description file in fmd format"
399 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
402 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
403 but in some cases more complex setups are required.
404 When an fmd is specified, it overrides the default format.
406 config MAINBOARD_HAS_TPM2
410 There is a TPM device installed on the mainboard, and it is
411 compliant with version 2 TCG TPM specification. Could be connected
412 over LPC, SPI or I2C.
416 # load site-local kconfig to allow user specific defaults and overrides
417 source "site-local/Kconfig"
419 config SYSTEM_TYPE_LAPTOP
423 config CBFS_AUTOGEN_ATTRIBUTES
427 If this option is selected, every file in cbfs which has a constraint
428 regarding position or alignment will get an additional file attribute
429 which describes this constraint.
434 source "src/soc/*/*/Kconfig"
436 source "src/cpu/Kconfig"
437 comment "Northbridge"
438 source "src/northbridge/*/*/Kconfig"
439 comment "Southbridge"
440 source "src/southbridge/*/*/Kconfig"
442 source "src/superio/*/*/Kconfig"
443 comment "Embedded Controllers"
444 source "src/ec/acpi/Kconfig"
445 source "src/ec/*/*/Kconfig"
446 # FIXME move to vendorcode
447 source "src/drivers/intel/fsp1_0/Kconfig"
449 source "src/southbridge/intel/common/firmware/Kconfig"
450 source "src/vboot/Kconfig"
451 source "src/vendorcode/*/Kconfig"
453 source "src/arch/*/Kconfig"
457 source "src/device/Kconfig"
459 menu "Generic Drivers"
460 source "src/drivers/*/Kconfig"
461 source "src/drivers/*/*/Kconfig"
464 source "src/acpi/Kconfig"
466 # This option is for the current boards/chipsets where SPI flash
467 # is not the boot device. Currently nearly all boards/chipsets assume
468 # SPI flash is the boot device.
469 config BOOT_DEVICE_NOT_SPI_FLASH
473 config BOOT_DEVICE_SPI_FLASH
475 default y if !BOOT_DEVICE_NOT_SPI_FLASH
478 config BOOT_DEVICE_MEMORY_MAPPED
480 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
483 Inform system if SPI is memory-mapped or not.
485 config BOOT_DEVICE_SUPPORTS_WRITES
489 Indicate that the platform has writable boot device
499 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
500 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
502 Enable this option to enable TPM support in coreboot.
508 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
509 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
511 Enable this option to enable TPM2 support in coreboot.
521 default 0x1000 if ARCH_X86
528 config MMCONF_SUPPORT_DEFAULT
532 config MMCONF_SUPPORT
536 source "src/console/Kconfig"
538 config HAVE_ACPI_RESUME
542 config RESUME_PATH_SAME_AS_BOOT
544 default y if ARCH_X86
545 depends on HAVE_ACPI_RESUME
547 This option indicates that when a system resumes it takes the
548 same path as a regular boot. e.g. an x86 system runs from the
549 reset vector at 0xfffffff0 on both resume and warm/cold boot.
551 config HAVE_HARD_RESET
555 This variable specifies whether a given board has a hard_reset
556 function, no matter if it's provided by board code or chipset code.
558 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
560 depends on EARLY_CBMEM_INIT
563 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
565 depends on EARLY_CBMEM_INIT
568 This should be enabled on certain plaforms, such as the AMD
569 SR565x, that cannot handle concurrent CBFS accesses from
570 multiple APs during early startup.
572 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
574 depends on EARLY_CBMEM_INIT
577 config HAVE_MONOTONIC_TIMER
580 The board/chipset provides a monotonic timer.
582 config GENERIC_UDELAY
584 depends on HAVE_MONOTONIC_TIMER
586 The board/chipset uses a generic udelay function utilizing the
591 depends on HAVE_MONOTONIC_TIMER
593 Provide a timer queue for performing time-based callbacks.
595 config COOP_MULTITASKING
597 depends on TIMER_QUEUE && ARCH_X86
599 Cooperative multitasking allows callbacks to be multiplexed on the
600 main thread of ramstage. With this enabled it allows for multiple
601 execution paths to take place when they have udelay() calls within
607 depends on COOP_MULTITASKING
609 How many execution threads to cooperatively multitask with.
611 config HAVE_OPTION_TABLE
615 This variable specifies whether a given board has a cmos.layout
616 file containing NVRAM/CMOS bit definitions.
617 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
623 config HAVE_SMI_HANDLER
627 config PCI_IO_CFG_EXT
635 config CACHE_ROM_SIZE_OVERRIDE
639 # TODO: Can probably be removed once all chipsets have kconfig options for it.
644 config USE_WATCHDOG_ON_BOOT
652 Build board-specific VGA code.
658 Enable Unified Memory Architecture for graphics.
660 config HAVE_ACPI_TABLES
663 This variable specifies whether a given board has ACPI table support.
664 It is usually set in mainboard/*/Kconfig.
669 This variable specifies whether a given board has MP table support.
670 It is usually set in mainboard/*/Kconfig.
671 Whether or not the MP table is actually generated by coreboot
672 is configurable by the user via GENERATE_MP_TABLE.
674 config HAVE_PIRQ_TABLE
677 This variable specifies whether a given board has PIRQ table support.
678 It is usually set in mainboard/*/Kconfig.
679 Whether or not the PIRQ table is actually generated by coreboot
680 is configurable by the user via GENERATE_PIRQ_TABLE.
682 config MAX_PIRQ_LINKS
686 This variable specifies the number of PIRQ interrupt links which are
687 routable. On most chipsets, this is 4, INTA through INTD. Some
688 chipsets offer more than four links, commonly up to INTH. They may
689 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
690 table specifies links greater than 4, pirq_route_irqs will not
691 function properly, unless this variable is correctly set.
701 Build support for NHLT (non HD Audio) ACPI table generation.
703 #These Options are here to avoid "undefined" warnings.
704 #The actual selection and help texts are in the following menu.
708 config GENERATE_MP_TABLE
709 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
711 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
713 Generate an MP table (conforming to the Intel MultiProcessor
714 specification 1.4) for this board.
718 config GENERATE_PIRQ_TABLE
719 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
721 default HAVE_PIRQ_TABLE
723 Generate a PIRQ table for this board.
727 config GENERATE_SMBIOS_TABLES
729 bool "Generate SMBIOS tables"
732 Generate SMBIOS tables for this board.
736 config SMBIOS_PROVIDED_BY_MOBO
740 config MAINBOARD_SERIAL_NUMBER
741 string "SMBIOS Serial Number"
742 depends on GENERATE_SMBIOS_TABLES
743 depends on !SMBIOS_PROVIDED_BY_MOBO
746 The Serial Number to store in SMBIOS structures.
748 config MAINBOARD_VERSION
749 string "SMBIOS Version Number"
750 depends on GENERATE_SMBIOS_TABLES
751 depends on !SMBIOS_PROVIDED_BY_MOBO
754 The Version Number to store in SMBIOS structures.
756 config MAINBOARD_SMBIOS_MANUFACTURER
757 string "SMBIOS Manufacturer"
758 depends on GENERATE_SMBIOS_TABLES
759 depends on !SMBIOS_PROVIDED_BY_MOBO
760 default MAINBOARD_VENDOR
762 Override the default Manufacturer stored in SMBIOS structures.
764 config MAINBOARD_SMBIOS_PRODUCT_NAME
765 string "SMBIOS Product name"
766 depends on GENERATE_SMBIOS_TABLES
767 depends on !SMBIOS_PROVIDED_BY_MOBO
768 default MAINBOARD_PART_NUMBER
770 Override the default Product name stored in SMBIOS structures.
774 source "payloads/Kconfig"
778 # TODO: Better help text and detailed instructions.
780 bool "GDB debugging support"
782 depends on CONSOLE_SERIAL
784 If enabled, you will be able to set breakpoints for gdb debugging.
785 See src/arch/x86/lib/c_start.S for details.
788 bool "Wait for a GDB connection"
792 If enabled, coreboot will wait for a GDB connection.
795 bool "Halt when hitting a BUG() or assertion error"
798 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
801 bool "Output verbose CBFS debug messages"
804 This option enables additional CBFS related debug messages.
806 config HAVE_DEBUG_RAM_SETUP
809 config DEBUG_RAM_SETUP
810 bool "Output verbose RAM init debug messages"
812 depends on HAVE_DEBUG_RAM_SETUP
814 This option enables additional RAM init related debug messages.
815 It is recommended to enable this when debugging issues on your
816 board which might be RAM init related.
818 Note: This option will increase the size of the coreboot image.
822 config HAVE_DEBUG_CAR
827 depends on HAVE_DEBUG_CAR
829 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
830 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
831 # printk(BIOS_DEBUG, ...) calls.
833 bool "Output verbose Cache-as-RAM debug messages"
835 depends on HAVE_DEBUG_CAR
837 This option enables additional CAR related debug messages.
841 bool "Check PIRQ table consistency"
843 depends on GENERATE_PIRQ_TABLE
847 config HAVE_DEBUG_SMBUS
851 bool "Output verbose SMBus debug messages"
853 depends on HAVE_DEBUG_SMBUS
855 This option enables additional SMBus (and SPD) debug messages.
857 Note: This option will increase the size of the coreboot image.
862 bool "Output verbose SMI debug messages"
864 depends on HAVE_SMI_HANDLER
865 select SPI_FLASH_SMM if SPI_CONSOLE
867 This option enables additional SMI related debug messages.
869 Note: This option will increase the size of the coreboot image.
873 config DEBUG_SMM_RELOCATION
874 bool "Debug SMM relocation code"
876 depends on HAVE_SMI_HANDLER
878 This option enables additional SMM handler relocation related
881 Note: This option will increase the size of the coreboot image.
885 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
886 # printk(BIOS_DEBUG, ...) calls.
888 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
892 This option enables additional malloc related debug messages.
894 Note: This option will increase the size of the coreboot image.
898 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
899 # printk(BIOS_DEBUG, ...) calls.
901 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
905 This option enables additional ACPI related debug messages.
907 Note: This option will slightly increase the size of the coreboot image.
911 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
912 # printk(BIOS_DEBUG, ...) calls.
913 config REALMODE_DEBUG
914 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
917 depends on PCI_OPTION_ROM_RUN_REALMODE
919 This option enables additional x86emu related debug messages.
921 Note: This option will increase the time to emulate a ROM.
926 bool "Output verbose x86emu debug messages"
928 depends on PCI_OPTION_ROM_RUN_YABEL
930 This option enables additional x86emu related debug messages.
932 Note: This option will increase the size of the coreboot image.
936 config X86EMU_DEBUG_JMP
937 bool "Trace JMP/RETF"
939 depends on X86EMU_DEBUG
941 Print information about JMP and RETF opcodes from x86emu.
943 Note: This option will increase the size of the coreboot image.
947 config X86EMU_DEBUG_TRACE
948 bool "Trace all opcodes"
950 depends on X86EMU_DEBUG
952 Print _all_ opcodes that are executed by x86emu.
954 WARNING: This will produce a LOT of output and take a long time.
956 Note: This option will increase the size of the coreboot image.
960 config X86EMU_DEBUG_PNP
961 bool "Log Plug&Play accesses"
963 depends on X86EMU_DEBUG
965 Print Plug And Play accesses made by option ROMs.
967 Note: This option will increase the size of the coreboot image.
971 config X86EMU_DEBUG_DISK
974 depends on X86EMU_DEBUG
976 Print Disk I/O related messages.
978 Note: This option will increase the size of the coreboot image.
982 config X86EMU_DEBUG_PMM
985 depends on X86EMU_DEBUG
987 Print messages related to POST Memory Manager (PMM).
989 Note: This option will increase the size of the coreboot image.
994 config X86EMU_DEBUG_VBE
995 bool "Debug VESA BIOS Extensions"
997 depends on X86EMU_DEBUG
999 Print messages related to VESA BIOS Extension (VBE) functions.
1001 Note: This option will increase the size of the coreboot image.
1005 config X86EMU_DEBUG_INT10
1006 bool "Redirect INT10 output to console"
1008 depends on X86EMU_DEBUG
1010 Let INT10 (i.e. character output) calls print messages to debug output.
1012 Note: This option will increase the size of the coreboot image.
1016 config X86EMU_DEBUG_INTERRUPTS
1017 bool "Log intXX calls"
1019 depends on X86EMU_DEBUG
1021 Print messages related to interrupt handling.
1023 Note: This option will increase the size of the coreboot image.
1027 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1028 bool "Log special memory accesses"
1030 depends on X86EMU_DEBUG
1032 Print messages related to accesses to certain areas of the virtual
1033 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1035 Note: This option will increase the size of the coreboot image.
1039 config X86EMU_DEBUG_MEM
1040 bool "Log all memory accesses"
1042 depends on X86EMU_DEBUG
1044 Print memory accesses made by option ROM.
1045 Note: This also includes accesses to fetch instructions.
1047 Note: This option will increase the size of the coreboot image.
1051 config X86EMU_DEBUG_IO
1052 bool "Log IO accesses"
1054 depends on X86EMU_DEBUG
1056 Print I/O accesses made by option ROM.
1058 Note: This option will increase the size of the coreboot image.
1062 config X86EMU_DEBUG_TIMINGS
1063 bool "Output timing information"
1065 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1067 Print timing information needed by i915tool.
1072 bool "Output verbose TPM debug messages"
1074 depends on TPM || TPM2
1076 This option enables additional TPM related debug messages.
1078 config DEBUG_SPI_FLASH
1079 bool "Output verbose SPI flash debug messages"
1081 depends on SPI_FLASH
1083 This option enables additional SPI flash related debug messages.
1085 config DEBUG_USBDEBUG
1086 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1090 This option enables additional USB 2.0 debug dongle related messages.
1092 Select this to debug the connection of usbdebug dongle. Note that
1093 you need some other working console to receive the messages.
1095 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1096 # Only visible with the right southbridge and loglevel.
1097 config DEBUG_INTEL_ME
1098 bool "Verbose logging for Intel Management Engine"
1101 Enable verbose logging for Intel Management Engine driver that
1102 is present on Intel 6-series chipsets.
1106 bool "Trace function calls"
1109 If enabled, every function will print information to console once
1110 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1111 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1112 of calling function. Please note some printk related functions
1113 are omitted from trace to have good looking console dumps.
1115 config DEBUG_COVERAGE
1116 bool "Debug code coverage"
1120 If enabled, the code coverage hooks in coreboot will output some
1121 information about the coverage data that is dumped.
1123 config DEBUG_BOOT_STATE
1124 bool "Debug boot state machine"
1127 Control debugging of the boot state machine. When selected displays
1128 the state boundaries in ramstage.
1130 config DEBUG_PRINT_PAGE_TABLES
1131 bool "Print the page tables after construction"
1133 depends on ARCH_RISCV
1135 After the page tables have been built, print them on the debug
1138 config DEBUG_ADA_CODE
1139 bool "Compile debug code in Ada sources"
1142 Add the compiler switch `-gnata` to compile code guarded by
1147 # These probably belong somewhere else, but they are needed somewhere.
1148 config ENABLE_APIC_EXT_ID
1152 config WARNINGS_ARE_ERRORS
1156 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1157 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1158 # mutually exclusive. One of these options must be selected in the
1159 # mainboard Kconfig if the chipset supports enabling and disabling of
1160 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1161 # in mainboard/Kconfig to know if the button should be enabled or not.
1163 config POWER_BUTTON_DEFAULT_ENABLE
1166 Select when the board has a power button which can optionally be
1167 disabled by the user.
1169 config POWER_BUTTON_DEFAULT_DISABLE
1172 Select when the board has a power button which can optionally be
1173 enabled by the user, e.g. when the board ships with a jumper over
1174 the power switch contacts.
1176 config POWER_BUTTON_FORCE_ENABLE
1179 Select when the board requires that the power button is always
1182 config POWER_BUTTON_FORCE_DISABLE
1185 Select when the board requires that the power button is always
1186 disabled, e.g. when it has been hardwired to ground.
1188 config POWER_BUTTON_IS_OPTIONAL
1190 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1191 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1193 Internal option that controls ENABLE_POWER_BUTTON visibility.
1199 Internal option that controls whether we compile in register scripts.
1201 config MAX_REBOOT_CNT
1205 Internal option that sets the maximum number of bootblock executions allowed
1206 with the normal image enabled before assuming the normal image is defective
1207 and switching to the fallback image.
1213 This is the part of the ROM actually managed by CBFS. Set it to be
1214 equal to the full ROM size if that hasn't been overridden by the
1215 chipset or mainboard.
1217 config CREATE_BOARD_CHECKLIST
1221 When selected, creates a webpage showing the implementation status for
1222 the board. Routines highlighted in green are complete, yellow are
1223 optional and red are required and must be implemented. A table is
1224 produced for each stage of the boot process except the bootblock. The
1225 red items may be used as an implementation checklist for the board.
1227 config MAKE_CHECKLIST_PUBLIC
1231 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1232 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1235 config CHECKLIST_DATA_FILE_LOCATION
1238 Location of the <stage>_complete.dat and <stage>_optional.dat files
1239 that are consumed during checklist processing. <stage>_complete.dat
1240 contains the symbols that are expected to be in the resulting image.
1241 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1242 a list of weak symbols which the resulting image may consume. Other
1243 symbols contained only in <stage>_complete.dat will be flagged as
1244 required and not implemented if a weak implementation is found in the
1250 Selected by features that use Ada code in ramstage.