src/soc/sifive/fu540/ux00ddr.h

   1 /* SPDX-License-Identifier: Apache-2.0 */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3 /* See the file LICENSE for further information */
   4
   5 #ifndef _SIFIVE_UX00DDR_H
   6 #define _SIFIVE_UX00DDR_H
   7
   8 #ifndef __ASSEMBLER__
   9
  10 #include <stdint.h>
  11 #include <stddef.h>
  12
  13 #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
  14
  15 #define DRAM_CLASS_OFFSET                   8
  16 #define DRAM_CLASS_DDR4                     0xA
  17 #define OPTIMAL_RMODW_EN_OFFSET             0
  18 #define DISABLE_RD_INTERLEAVE_OFFSET        16
  19 #define OUT_OF_RANGE_OFFSET                 1
  20 #define MULTIPLE_OUT_OF_RANGE_OFFSET        2
  21 #define PORT_COMMAND_CHANNEL_ERROR_OFFSET   7
  22 #define MC_INIT_COMPLETE_OFFSET             8
  23 #define LEVELING_OPERATION_COMPLETED_OFFSET 22
  24 #define DFI_PHY_WRLELV_MODE_OFFSET          24
  25 #define DFI_PHY_RDLVL_MODE_OFFSET           24
  26 #define DFI_PHY_RDLVL_GATE_MODE_OFFSET      0
  27 #define VREF_EN_OFFSET                      24
  28 #define PORT_ADDR_PROTECTION_EN_OFFSET      0
  29 #define AXI0_ADDRESS_RANGE_ENABLE           8
  30 #define AXI0_RANGE_PROT_BITS_0_OFFSET       24
  31 #define RDLVL_EN_OFFSET                     16
  32 #define RDLVL_GATE_EN_OFFSET                24
  33 #define WRLVL_EN_OFFSET                     0
  34
  35 #define PHY_RX_CAL_DQ0_0_OFFSET             0
  36 #define PHY_RX_CAL_DQ1_0_OFFSET             16
  37
  38 static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) {
  39   unsigned int i;
  40   for (i=1152;i<=1214;i++) {
  41     uint32_t physet = physettings[i];
  42     /*if (physet!=0)*/ ddrphyreg[i] = physet;
  43   }
  44   for (i=0;i<=1151;i++) {
  45     uint32_t physet = physettings[i];
  46     /*if (physet!=0)*/ ddrphyreg[i] = physet;
  47   }
  48 }
  49
  50
  51 static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
  52   volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr;
  53   volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t));
  54
  55   unsigned int i;
  56   for (i=0;i<=264;i++) {
  57     uint32_t ctlset = ctlsettings[i];
  58     /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
  59   }
  60
  61   phy_reset(ddrphyreg, physettings);
  62 }
  63
  64 static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) {
  65   // START register at ddrctl register base offset 0
  66   uint32_t regdata = _REG32(0<<2, ahbregaddr);
  67   regdata |= 0x1;
  68   _REG32(0<<2, ahbregaddr) = regdata;
  69   // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210
  70   while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
  71
  72   // Disable the BusBlocker in front of the controller AXI slave ports
  73   volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr;
  74   filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
  75   //                ^^ RWX + TOR
  76 }
  77
  78 static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) {
  79   // Mask off Bit 8 of Interrupt Status
  80   // Bit [8] The MC initialization has been completed
  81   _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET);
  82 }
  83
  84 static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) {
  85   // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
  86   // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured
  87   // Bit [1] A memory access outside the defined PHYSICAL memory space has occured
  88   _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
  89 }
  90
  91 static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
  92   // Mask off Bit 7 of Interrupt Status
  93   // Bit [7] An error occured on the port command channel
  94   _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET);
  95 }
  96
  97 static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) {
  98   // Mask off Bit 22 of Interrupt Status
  99   // Bit [22] The leveling operation has completed
 100   _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET);
 101 }
 102
 103 static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) {
 104   _REG32(209<<2, ahbregaddr) = 0x0;
 105   size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1;
 106   _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks);
 107   _REG32(212<<2, ahbregaddr) = 0x0;
 108   _REG32(214<<2, ahbregaddr) = 0x0;
 109   _REG32(216<<2, ahbregaddr) = 0x0;
 110   _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
 111   _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
 112   _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
 113   _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
 114
 115 }
 116
 117 static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
 118   _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET);
 119 }
 120
 121 static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) {
 122   _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET));
 123 }
 124
 125 static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) {
 126   _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET));
 127 }
 128
 129 static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) {
 130   _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET);
 131   _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET);
 132 }
 133
 134 static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) {
 135   _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET);
 136   _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET);
 137 }
 138
 139 static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) {
 140   _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET);
 141 }
 142
 143 static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) {
 144   return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
 145 }
 146
 147 static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) {
 148   // return bitmask of failed lanes
 149
 150   size_t ddrphyreg = ahbregaddr + 0x2000;
 151
 152   uint64_t fails=0;
 153   uint32_t slicebase = 0;
 154   uint32_t dq = 0;
 155
 156   // check errata condition
 157   for (uint32_t slice = 0; slice < 8; slice++) {
 158     uint32_t regbase = slicebase + 34;
 159     for (uint32_t reg = 0 ; reg < 4; reg++) {
 160       uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg);
 161       for (uint32_t bit = 0; bit < 2; bit++) {
 162         uint32_t phy_rx_cal_dqn_0_offset;
 163
 164         if (bit==0) {
 165           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
 166         }else{
 167           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
 168         }
 169
 170         uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
 171         uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
 172
 173         uint8_t failc0 = ((down == 0) && (up == 0x3F));
 174         uint8_t failc1 = ((up == 0) && (down == 0x3F));
 175
 176         // print error message on failure
 177         if (failc0 || failc1) {
 178           //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
 179           fails |= (1<<dq);
 180           char slicelsc = '0';
 181           char slicemsc = '0';
 182           slicelsc += (dq % 10);
 183           slicemsc += (dq / 10);
 184           //uart_puts((void*) UART0_CTRL_ADDR, "S ");
 185           //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc);
 186           //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc);
 187           //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U");
 188           //else uart_puts((void*) UART0_CTRL_ADDR, "D");
 189           //uart_puts((void*) UART0_CTRL_ADDR, "\n");
 190         }
 191         dq++;
 192       }
 193     }
 194     slicebase+=128;
 195   }
 196   return (0);
 197 }
 198
 199 #endif
 200
 201 #endif