src/soc/samsung/exynos5420/spi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <device/mmio.h>
  16 #include <assert.h>
  17 #include <console/console.h>
  18 #include <soc/cpu.h>
  19 #include <soc/spi.h>
  20 #include <spi-generic.h>
  21 #include <string.h>
  22 #include <symbols.h>
  23
  24 #define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535)
  25
  26 #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
  27 # define DEBUG_SPI(x,...)       printk(BIOS_DEBUG, "EXYNOS_SPI: " x)
  28 #else
  29 # define DEBUG_SPI(x,...)
  30 #endif
  31
  32 struct exynos_spi_slave {
  33         struct spi_slave slave;
  34         struct exynos_spi *regs;
  35         int initialized;
  36 };
  37
  38 /* TODO(hungte) Move the SPI param list to per-board configuration, probably
  39  * Kconfig or mainboard.c */
  40 static struct exynos_spi_slave exynos_spi_slaves[3] = {
  41         // SPI 0
  42         {
  43                 .slave = { .bus = 0, },
  44                 .regs = (void *)EXYNOS5_SPI0_BASE,
  45         },
  46         // SPI 1
  47         {
  48                 .slave = { .bus = 1, },
  49                 .regs = (void *)EXYNOS5_SPI1_BASE,
  50         },
  51         // SPI 2
  52         {
  53                 .slave = { .bus = 2, },
  54                 .regs = (void *)EXYNOS5_SPI2_BASE,
  55         },
  56 };
  57
  58 static inline struct exynos_spi_slave *to_exynos_spi(const struct spi_slave *slave)
  59 {
  60         return &exynos_spi_slaves[slave->bus];
  61 }
  62
  63 static void spi_sw_reset(struct exynos_spi *regs, int word)
  64 {
  65         const uint32_t orig_mode_cfg = read32(&regs->mode_cfg);
  66         uint32_t mode_cfg = orig_mode_cfg;
  67         const uint32_t orig_swap_cfg = read32(&regs->swap_cfg);
  68         uint32_t swap_cfg = orig_swap_cfg;
  69
  70         mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK);
  71         if (word) {
  72                 mode_cfg |= SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD;
  73                 swap_cfg |= SPI_RX_SWAP_EN |
  74                             SPI_RX_BYTE_SWAP |
  75                             SPI_RX_HWORD_SWAP |
  76                             SPI_TX_SWAP_EN |
  77                             SPI_TX_BYTE_SWAP |
  78                             SPI_TX_HWORD_SWAP;
  79         } else {
  80                 mode_cfg |= SPI_MODE_CH_WIDTH_BYTE | SPI_MODE_BUS_WIDTH_BYTE;
  81                 swap_cfg = 0;
  82         }
  83
  84         if (mode_cfg != orig_mode_cfg)
  85                 write32(&regs->mode_cfg, mode_cfg);
  86         if (swap_cfg != orig_swap_cfg)
  87                 write32(&regs->swap_cfg, swap_cfg);
  88
  89         clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  90         setbits32(&regs->ch_cfg, SPI_CH_RST);
  91         clrbits32(&regs->ch_cfg, SPI_CH_RST);
  92         setbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  93 }
  94
  95 static void exynos_spi_init(struct exynos_spi *regs)
  96 {
  97         // Set FB_CLK_SEL.
  98         write32(&regs->fb_clk, SPI_FB_DELAY_180);
  99         // CPOL: Active high.
 100         clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);
 101
 102         // Clear rx and tx channel if set previously.
 103         clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 104
 105         setbits32(&regs->swap_cfg,
 106                      SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP);
 107         clrbits32(&regs->ch_cfg, SPI_CH_HS_EN);
 108
 109         // Do a soft reset, which will also enable both channels.
 110         spi_sw_reset(regs, 1);
 111 }
 112
 113 static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 114 {
 115         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 116         // TODO(hungte) Add some delay if too many transactions happen at once.
 117         clrbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 118         return 0;
 119 }
 120
 121 static void spi_transfer(struct exynos_spi *regs, void *in, const void *out,
 122                          size_t size)
 123 {
 124         u8 *inb = in;
 125         const u8 *outb = out;
 126
 127         size_t width = (size % 4) ? 1 : 4;
 128
 129         while (size) {
 130                 size_t packets = size / width;
 131                 // The packet count field is 16 bits wide.
 132                 packets = MIN(packets, (1 << 16) - 1);
 133
 134                 size_t out_bytes, in_bytes;
 135                 out_bytes = in_bytes = packets * width;
 136
 137                 spi_sw_reset(regs, width == 4);
 138                 write32(&regs->pkt_cnt, packets | SPI_PACKET_CNT_EN);
 139
 140                 while (out_bytes || in_bytes) {
 141                         uint32_t spi_sts = read32(&regs->spi_sts);
 142                         int rx_lvl = ((spi_sts >> 15) & 0x1ff);
 143                         int tx_lvl = ((spi_sts >> 6) & 0x1ff);
 144
 145                         if (tx_lvl < 32 && tx_lvl < out_bytes) {
 146                                 uint32_t data = 0xffffffff;
 147
 148                                 if (outb) {
 149                                         memcpy(&data, outb, width);
 150                                         outb += width;
 151                                 }
 152                                 write32(&regs->tx_data, data);
 153
 154                                 out_bytes -= width;
 155                         }
 156
 157                         if (rx_lvl >= width) {
 158                                 uint32_t data = read32(&regs->rx_data);
 159
 160                                 if (inb) {
 161                                         memcpy(inb, &data, width);
 162                                         inb += width;
 163                                 }
 164
 165                                 in_bytes -= width;
 166                         }
 167                 }
 168
 169                 size -= packets * width;
 170         }
 171 }
 172
 173 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out,
 174              void *din, size_t bytes_in)
 175 {
 176         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 177
 178         if (bytes_out && bytes_in) {
 179                 size_t min_size = MIN(bytes_out, bytes_in);
 180
 181                 spi_transfer(regs, din, dout, min_size);
 182
 183                 bytes_out -= min_size;
 184                 bytes_in -= min_size;
 185
 186                 din = (uint8_t *)din + min_size;
 187                 dout = (const uint8_t *)dout + min_size;
 188         }
 189
 190         if (bytes_in)
 191                 spi_transfer(regs, din, NULL, bytes_in);
 192         else if (bytes_out)
 193                 spi_transfer(regs, NULL, dout, bytes_out);
 194
 195         return 0;
 196 }
 197
 198 static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 199 {
 200         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 201         setbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 202 }
 203
 204 static int spi_ctrlr_setup(const struct spi_slave *slave)
 205 {
 206         ASSERT(slave->bus < 3);
 207         struct exynos_spi_slave *eslave;
 208
 209         eslave = to_exynos_spi(slave);
 210         if (!eslave->initialized) {
 211                 exynos_spi_init(eslave->regs);
 212                 eslave->initialized = 1;
 213         }
 214         return 0;
 215 }
 216
 217 static const struct spi_ctrlr spi_ctrlr = {
 218         .setup = spi_ctrlr_setup,
 219         .claim_bus = spi_ctrlr_claim_bus,
 220         .release_bus = spi_ctrlr_release_bus,
 221         .xfer = spi_ctrlr_xfer,
 222         .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE,
 223 };
 224
 225 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 226         {
 227                 .ctrlr = &spi_ctrlr,
 228                 .bus_start = 0,
 229                 .bus_end = 2,
 230         },
 231 };
 232
 233 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
 234
 235 static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
 236                            uint32_t off)
 237 {
 238         struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 239         u32 command;
 240         spi_claim_bus(slave);
 241
 242         // Send address.
 243         ASSERT(off < (1 << 24));
 244         command = htonl(SF_READ_DATA_CMD << 24 | off);
 245         spi_transfer(regs, NULL, &command, sizeof(command));
 246
 247         // Read the data.
 248         spi_transfer(regs, dest, NULL, len);
 249         spi_release_bus(slave);
 250
 251         return len;
 252 }
 253
 254 static struct exynos_spi_slave *boot_slave;
 255
 256 static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
 257                                         size_t offset, size_t count)
 258 {
 259         DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
 260         return exynos_spi_read(&boot_slave->slave, dest, count, offset);
 261 }
 262
 263 static void *exynos_spi_map(const struct region_device *rdev,
 264                                         size_t offset, size_t count)
 265 {
 266         DEBUG_SPI("exynos_spi_cbfs_map\n");
 267         // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
 268         // requires buffer memory address to be aligned.
 269         if (count % 4)
 270                 count += 4 - (count % 4);
 271         return mmap_helper_rdev_mmap(rdev, offset, count);
 272 }
 273
 274 static const struct region_device_ops exynos_spi_ops = {
 275         .mmap = exynos_spi_map,
 276         .munmap = mmap_helper_rdev_munmap,
 277         .readat = exynos_spi_readat,
 278 };
 279
 280 static struct mmap_helper_region_device mdev =
 281         MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE);
 282
 283 void exynos_init_spi_boot_device(void)
 284 {
 285         boot_slave = &exynos_spi_slaves[1];
 286
 287         mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache));
 288 }
 289
 290 const struct region_device *exynos_spi_boot_device(void)
 291 {
 292         return &mdev.rdev;
 293 }