src/soc/samsung/exynos5420/clock_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 /* Clock setup for SMDK5420 board based on EXYNOS5 */
  16
  17 #include <device/mmio.h>
  18 #include <soc/clk.h>
  19 #include <soc/cpu.h>
  20 #include <soc/dp.h>
  21 #include <soc/dmc.h>
  22 #include <soc/setup.h>
  23
  24 void system_clock_init(void)
  25 {
  26         u32 val;
  27
  28         /* Turn on the MCT as early as possible. */
  29         exynos_mct->g_tcon |= (1 << 8);
  30
  31         /* PLL locktime */
  32         write32(&exynos_clock->apll_lock, APLL_LOCK_VAL);
  33         write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL);
  34         write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL);
  35         write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL);
  36         write32(&exynos_clock->dpll_lock, DPLL_LOCK_VAL);
  37         write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL);
  38         write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL);
  39         write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL);
  40         write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL);
  41         write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
  42         write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
  43
  44         setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
  45
  46         write32(&exynos_clock->clk_src_top6, 0);
  47
  48         write32(&exynos_clock->clk_src_cdrex, 0);
  49         write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
  50         write32(&exynos_clock->clk_div_cpu1, HPM_RATIO);
  51         write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL);
  52
  53         /* switch A15 clock source to OSC clock before changing APLL */
  54         clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
  55
  56         /* Set APLL */
  57         write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
  58         val = set_pll(225, 3, 0);       /* FOUT=1800MHz */
  59         write32(&exynos_clock->apll_con0, val);
  60         while ((read32(&exynos_clock->apll_con0) & PLL_LOCKED) == 0)
  61                 ;
  62
  63         /* now it is safe to switch to APLL */
  64         setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
  65
  66         write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
  67         write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL);
  68
  69         /* switch A7 clock source to OSC clock before changing KPLL */
  70         clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
  71
  72         /* Set KPLL*/
  73         write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL);
  74         val = set_pll(0x190, 0x4, 0x2);
  75         write32(&exynos_clock->kpll_con0, val);
  76         while ((read32(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0)
  77                 ;
  78
  79         /* now it is safe to switch to KPLL */
  80         setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
  81
  82         /* Set MPLL */
  83         write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
  84         val = set_pll(0xc8, 0x3, 0x1);
  85         write32(&exynos_clock->mpll_con0, val);
  86         while ((read32(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0)
  87                 ;
  88
  89         /* Set DPLL */
  90         write32(&exynos_clock->dpll_con1, DPLL_CON1_VAL);
  91         val = set_pll(0x190, 0x4, 0x2);
  92         write32(&exynos_clock->dpll_con0, val);
  93         while ((read32(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0)
  94                 ;
  95
  96         /* Set EPLL */
  97         write32(&exynos_clock->epll_con2, EPLL_CON2_VAL);
  98         write32(&exynos_clock->epll_con1, EPLL_CON1_VAL);
  99         val = set_pll(0x64, 0x2, 0x1);
 100         write32(&exynos_clock->epll_con0, val);
 101         while ((read32(&exynos_clock->epll_con0) & PLL_LOCKED) == 0)
 102                 ;
 103
 104         /* Set CPLL */
 105         write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL);
 106         val = set_pll(0xde, 0x4, 0x1);
 107         write32(&exynos_clock->cpll_con0, val);
 108         while ((read32(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0)
 109                 ;
 110
 111         /* Set IPLL */
 112         write32(&exynos_clock->ipll_con1, IPLL_CON1_VAL);
 113         val = set_pll(0xB9, 0x3, 0x2);
 114         write32(&exynos_clock->ipll_con0, val);
 115         while ((read32(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0)
 116                 ;
 117
 118         /* Set VPLL */
 119         write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL);
 120         val = set_pll(0xd7, 0x3, 0x2);
 121         write32(&exynos_clock->vpll_con0, val);
 122         while ((read32(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0)
 123                 ;
 124
 125         /* Set BPLL */
 126         write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL);
 127         val = set_pll(0xc8, 0x3, 0x1);
 128         write32(&exynos_clock->bpll_con0, val);
 129         while ((read32(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0)
 130                 ;
 131
 132         /* Set SPLL */
 133         write32(&exynos_clock->spll_con1, SPLL_CON1_VAL);
 134         val = set_pll(200, 0x3, 0x2);   /* 400MHz */
 135         write32(&exynos_clock->spll_con0, val);
 136         while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
 137                 ;
 138
 139         /* We use RPLL as the source for FIMD video stream clock */
 140         write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL);
 141         write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL);
 142         /* computed by gabe from first principles; u-boot is probably
 143          * wrong again
 144          */
 145         val = set_pll(0xa0, 0x3, 0x2);
 146         write32(&exynos_clock->rpll_con0, val);
 147         /* note: this is a meaningless exercise. The hardware lock
 148          * detection does not work. So this just spins for some
 149          * time and is done. NO indication of success should attach
 150          * to this or any other spin on a con0 value.
 151          */
 152         while ((read32(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0)
 153                 ;
 154
 155         write32(&exynos_clock->clk_div_cdrex0, CLK_DIV_CDREX0_VAL);
 156         write32(&exynos_clock->clk_div_cdrex1, CLK_DIV_CDREX1_VAL);
 157
 158         write32(&exynos_clock->clk_src_top0, CLK_SRC_TOP0_VAL);
 159         write32(&exynos_clock->clk_src_top1, CLK_SRC_TOP1_VAL);
 160         write32(&exynos_clock->clk_src_top2, CLK_SRC_TOP2_VAL);
 161         write32(&exynos_clock->clk_src_top7, CLK_SRC_TOP7_VAL);
 162
 163         write32(&exynos_clock->clk_div_top0, CLK_DIV_TOP0_VAL);
 164         write32(&exynos_clock->clk_div_top1, CLK_DIV_TOP1_VAL);
 165         write32(&exynos_clock->clk_div_top2, CLK_DIV_TOP2_VAL);
 166
 167         write32(&exynos_clock->clk_src_top10, 0);
 168         write32(&exynos_clock->clk_src_top11, 0);
 169         write32(&exynos_clock->clk_src_top12, 0);
 170
 171         write32(&exynos_clock->clk_src_top3, CLK_SRC_TOP3_VAL);
 172         write32(&exynos_clock->clk_src_top4, CLK_SRC_TOP4_VAL);
 173         write32(&exynos_clock->clk_src_top5, CLK_SRC_TOP5_VAL);
 174
 175         /* DISP1 BLK CLK SELECTION */
 176         write32(&exynos_clock->clk_src_disp10, CLK_SRC_DISP1_0_VAL);
 177         write32(&exynos_clock->clk_div_disp10, CLK_DIV_DISP1_0_VAL);
 178
 179         /* AUDIO BLK */
 180         write32(&exynos_clock->clk_src_mau, AUDIO0_SEL_EPLL);
 181         write32(&exynos_clock->clk_div_mau, DIV_MAU_VAL);
 182
 183         /* FSYS */
 184         write32(&exynos_clock->clk_src_fsys, CLK_SRC_FSYS0_VAL);
 185         write32(&exynos_clock->clk_div_fsys0, CLK_DIV_FSYS0_VAL);
 186         write32(&exynos_clock->clk_div_fsys1, CLK_DIV_FSYS1_VAL);
 187         write32(&exynos_clock->clk_div_fsys2, CLK_DIV_FSYS2_VAL);
 188
 189         write32(&exynos_clock->clk_src_isp, CLK_SRC_ISP_VAL);
 190         write32(&exynos_clock->clk_div_isp0, CLK_DIV_ISP0_VAL);
 191         write32(&exynos_clock->clk_div_isp1, CLK_DIV_ISP1_VAL);
 192
 193         write32(&exynos_clock->clk_src_peric0, CLK_SRC_PERIC0_VAL);
 194         write32(&exynos_clock->clk_src_peric1, CLK_SRC_PERIC1_VAL);
 195
 196         write32(&exynos_clock->clk_div_peric0, CLK_DIV_PERIC0_VAL);
 197         write32(&exynos_clock->clk_div_peric1, CLK_DIV_PERIC1_VAL);
 198         write32(&exynos_clock->clk_div_peric2, CLK_DIV_PERIC2_VAL);
 199         write32(&exynos_clock->clk_div_peric3, CLK_DIV_PERIC3_VAL);
 200         write32(&exynos_clock->clk_div_peric4, CLK_DIV_PERIC4_VAL);
 201
 202         write32(&exynos_clock->clk_div_cperi1, CLK_DIV_CPERI1_VAL);
 203
 204         write32(&exynos_clock->clkdiv2_ratio, CLK_DIV2_RATIO);
 205         write32(&exynos_clock->clkdiv4_ratio, CLK_DIV4_RATIO);
 206         write32(&exynos_clock->clk_div_g2d, CLK_DIV_G2D);
 207
 208         write32(&exynos_clock->clk_src_cpu, CLK_SRC_CPU_VAL);
 209         write32(&exynos_clock->clk_src_top6, CLK_SRC_TOP6_VAL);
 210         write32(&exynos_clock->clk_src_cdrex, CLK_SRC_CDREX_VAL);
 211         write32(&exynos_clock->clk_src_kfc, CLK_SRC_KFC_VAL);
 212 }
 213
 214 void clock_gate(void)
 215 {
 216         /* Not implemented for now. */
 217 }