src/soc/samsung/exynos5250/dp-reg.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 /* Samsung DP (Display port) register interface driver. */
  16
  17 #include <device/mmio.h>
  18 #include <console/console.h>
  19 #include <delay.h>
  20 #include <soc/clk.h>
  21 #include <soc/cpu.h>
  22 #include <soc/dp.h>
  23 #include <soc/dp-core.h>
  24 #include <soc/fimd.h>
  25 #include <soc/periph.h>
  26 #include <timer.h>
  27
  28 void s5p_dp_reset(struct s5p_dp_device *dp)
  29 {
  30         u32 reg;
  31         struct exynos5_dp *base = dp->base;
  32
  33         write32(&base->dp_tx_sw_reset, RESET_DP_TX);
  34
  35         /* Stop Video */
  36         clrbits32(&base->video_ctl_1, VIDEO_EN);
  37         clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE);
  38
  39         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
  40                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
  41                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
  42         write32(&base->func_en_1, reg);
  43
  44         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
  45                 SERDES_FIFO_FUNC_EN_N |
  46                 LS_CLK_DOMAIN_FUNC_EN_N;
  47         write32(&base->func_en_2, reg);
  48
  49         udelay(20);
  50
  51         reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  52                 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  53
  54         write32(&base->lane_map, reg);
  55
  56         write32(&base->sys_ctl_1, 0x0);
  57         write32(&base->sys_ctl_2, 0x40);
  58         write32(&base->sys_ctl_3, 0x0);
  59         write32(&base->sys_ctl_4, 0x0);
  60
  61         write32(&base->pkt_send_ctl, 0x0);
  62         write32(&base->dp_hdcp_ctl, 0x0);
  63
  64         write32(&base->dp_hpd_deglitch_l, 0x5e);
  65         write32(&base->dp_hpd_deglitch_h, 0x1a);
  66
  67         write32(&base->dp_debug_ctl, 0x10);
  68
  69         write32(&base->dp_phy_test, 0x0);
  70
  71         write32(&base->dp_video_fifo_thrd, 0x0);
  72         write32(&base->dp_audio_margin, 0x20);
  73
  74         write32(&base->m_vid_gen_filter_th, 0x4);
  75         write32(&base->m_aud_gen_filter_th, 0x2);
  76
  77         write32(&base->soc_general_ctl, 0x00000101);
  78
  79         /* Set Analog Parameters */
  80         write32(&base->analog_ctl_1, 0x10);
  81         write32(&base->analog_ctl_2, 0x0C);
  82         write32(&base->analog_ctl_3, 0x85);
  83         write32(&base->pll_filter_ctl_1, 0x66);
  84         write32(&base->tx_amp_tuning_ctl, 0x0);
  85
  86         /* Set interrupt pin assertion polarity as high */
  87         write32(&base->int_ctl, INT_POL0 | INT_POL1);
  88
  89         /* Clear pending registers */
  90         write32(&base->common_int_sta_1, 0xff);
  91         write32(&base->common_int_sta_2, 0x4f);
  92         write32(&base->common_int_sta_3, 0xe0);
  93         write32(&base->common_int_sta_4, 0xe7);
  94         write32(&base->dp_int_sta, 0x63);
  95
  96         /* 0:mask,1: unmask */
  97         write32(&base->common_int_mask_1, 0x00);
  98         write32(&base->common_int_mask_2, 0x00);
  99         write32(&base->common_int_mask_3, 0x00);
 100         write32(&base->common_int_mask_4, 0x00);
 101         write32(&base->int_sta_mask, 0x00);
 102 }
 103
 104 unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp)
 105 {
 106         u32 reg;
 107
 108         reg = read32(&dp->base->dp_debug_ctl);
 109         if (reg & PLL_LOCK)
 110                 return PLL_LOCKED;
 111         else
 112                 return PLL_UNLOCKED;
 113 }
 114
 115 int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
 116 {
 117         u32 reg;
 118         struct stopwatch sw;
 119         struct exynos5_dp *base = dp->base;
 120
 121         write32(&base->dp_phy_pd, 0x00);
 122
 123         reg = PLL_LOCK_CHG;
 124         write32(&base->common_int_sta_1, reg);
 125
 126         clrbits32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL));
 127
 128         /* Power up PLL */
 129         if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 130
 131                 clrbits32(&base->dp_pll_ctl, DP_PLL_PD);
 132
 133                 stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);
 134
 135                 while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 136                         if (stopwatch_expired(&sw)) {
 137                                 printk(BIOS_ERR, "%s: PLL is not locked\n",
 138                                                 __func__);
 139                                 return -1;
 140                         }
 141                 }
 142         }
 143
 144         /* Enable Serdes FIFO function and Link symbol clock domain module */
 145         clrbits32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N |
 146                                 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N));
 147         return 0;
 148 }
 149
 150 void s5p_dp_init_aux(struct s5p_dp_device *dp)
 151 {
 152         u32 reg;
 153         struct exynos5_dp *base = dp->base;
 154
 155         /* Clear interrupts related to AUX channel */
 156         reg = RPLY_RECEIV | AUX_ERR;
 157         write32(&base->dp_int_sta, reg);
 158
 159         /* Disable AUX channel module */
 160         setbits32(&base->func_en_2, AUX_FUNC_EN_N);
 161
 162         /* Disable AUX transaction H/W retry */
 163         reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT;
 164         reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT;
 165         reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT);
 166         write32(&base->aux_hw_retry_ctl, reg);
 167
 168         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 169         reg = DEFER_CTRL_EN;
 170         reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT;
 171         write32(&base->aux_ch_defer_dtl, reg);
 172
 173         /* Enable AUX channel module */
 174         clrbits32(&base->func_en_2, AUX_FUNC_EN_N);
 175 }
 176
 177 int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
 178 {
 179         int reg;
 180         struct exynos5_dp *base = dp->base;
 181
 182         /* Enable AUX CH operation */
 183         setbits32(&base->aux_ch_ctl_2, AUX_EN);
 184
 185         /* Is AUX CH command reply received? */
 186         reg = read32(&base->dp_int_sta);
 187         while (!(reg & RPLY_RECEIV))
 188                 reg = read32(&base->dp_int_sta);
 189
 190         /* Clear interrupt source for AUX CH command reply */
 191         write32(&base->dp_int_sta, RPLY_RECEIV);
 192
 193         /* Clear interrupt source for AUX CH access error */
 194         reg = read32(&base->dp_int_sta);
 195         if (reg & AUX_ERR) {
 196                 printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: "
 197                                 "0x%02x\n", __func__, reg);
 198                 write32(&base->dp_int_sta, AUX_ERR);
 199                 return -1;
 200         }
 201
 202         /* Check AUX CH error access status */
 203         reg = read32(&base->dp_int_sta);
 204         if ((reg & AUX_STATUS_MASK) != 0) {
 205                 printk(BIOS_ERR, "AUX CH error happens: %d\n\n",
 206                         reg & AUX_STATUS_MASK);
 207                 return -1;
 208         }
 209
 210         return 0;
 211 }
 212
 213 int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
 214                                 unsigned int reg_addr,
 215                                 unsigned char data)
 216 {
 217         u32 reg;
 218         int i;
 219         int retval;
 220         struct exynos5_dp *base = dp->base;
 221
 222         for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 223                 /* Clear AUX CH data buffer */
 224                 write32(&base->buf_data_ctl, BUF_CLR);
 225
 226                 /* Select DPCD device address */
 227                 reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 228                 reg &= AUX_ADDR_7_0_MASK;
 229                 write32(&base->aux_addr_7_0, reg);
 230                 reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 231                 reg &= AUX_ADDR_15_8_MASK;
 232                 write32(&base->aux_addr_15_8, reg);
 233                 reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 234                 reg &= AUX_ADDR_19_16_MASK;
 235                 write32(&base->aux_addr_19_16, reg);
 236
 237                 /* Write data buffer */
 238                 reg = (unsigned int)data;
 239                 write32(&base->buf_data_0, reg);
 240
 241                 /*
 242                  * Set DisplayPort transaction and write 1 byte
 243                  * If bit 3 is 1, DisplayPort transaction.
 244                  * If Bit 3 is 0, I2C transaction.
 245                  */
 246                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 247                 write32(&base->aux_ch_ctl_1, reg);
 248
 249                 /* Start AUX transaction */
 250                 retval = s5p_dp_start_aux_transaction(dp);
 251                 if (retval == 0)
 252                         break;
 253                 else
 254                         printk(BIOS_DEBUG, "Aux Transaction fail!\n");
 255         }
 256
 257         return retval;
 258 }
 259
 260 int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 261                                 unsigned int reg_addr,
 262                                 unsigned char *data)
 263 {
 264         u32 reg;
 265         int i;
 266         int retval;
 267         struct exynos5_dp *base = dp->base;
 268
 269         for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 270                 /* Clear AUX CH data buffer */
 271                 write32(&base->buf_data_ctl, BUF_CLR);
 272
 273                 /* Select DPCD device address */
 274                 reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 275                 reg &= AUX_ADDR_7_0_MASK;
 276                 write32(&base->aux_addr_7_0, reg);
 277                 reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 278                 reg &= AUX_ADDR_15_8_MASK;
 279                 write32(&base->aux_addr_15_8, reg);
 280                 reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 281                 reg &= AUX_ADDR_19_16_MASK;
 282                 write32(&base->aux_addr_19_16, reg);
 283
 284                 /*
 285                  * Set DisplayPort transaction and read 1 byte
 286                  * If bit 3 is 1, DisplayPort transaction.
 287                  * If Bit 3 is 0, I2C transaction.
 288                  */
 289                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 290                 write32(&base->aux_ch_ctl_1, reg);
 291
 292                 /* Start AUX transaction */
 293                 retval = s5p_dp_start_aux_transaction(dp);
 294                 if (retval == 0)
 295                         break;
 296                 else
 297                         printk(BIOS_DEBUG, "Aux Transaction fail!\n");
 298         }
 299
 300         /* Read data buffer */
 301         if (!retval) {
 302                 reg = read32(&base->buf_data_0);
 303                 *data = (unsigned char)(reg & 0xff);
 304         }
 305
 306         return retval;
 307 }
 308
 309 void s5p_dp_init_video(struct s5p_dp_device *dp)
 310 {
 311         u32 reg;
 312         struct exynos5_dp *base = dp->base;
 313
 314         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 315         write32(&base->common_int_sta_1, reg);
 316
 317         reg = 0x0;
 318         write32(&base->sys_ctl_1, reg);
 319
 320         reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT;
 321         reg |= CHA_CTRL;
 322         write32(&base->sys_ctl_2, reg);
 323
 324         reg = 0x0;
 325         write32(&base->sys_ctl_3, reg);
 326 }
 327
 328 void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
 329                                         unsigned int color_depth,
 330                                         unsigned int color_space,
 331                                         unsigned int dynamic_range,
 332                                         unsigned int coeff)
 333 {
 334         u32 reg;
 335         struct exynos5_dp *base = dp->base;
 336
 337         /* Configure the input color depth, color space, dynamic range */
 338         reg = (dynamic_range << IN_D_RANGE_SHIFT) |
 339                 (color_depth << IN_BPC_SHIFT) |
 340                 (color_space << IN_COLOR_F_SHIFT);
 341         write32(&base->video_ctl_2, reg);
 342
 343         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 344         reg = read32(&base->video_ctl_3);
 345         reg &= ~IN_YC_COEFFI_MASK;
 346         if (coeff)
 347                 reg |= IN_YC_COEFFI_ITU709;
 348         else
 349                 reg |= IN_YC_COEFFI_ITU601;
 350         write32(&base->video_ctl_3, reg);
 351 }
 352
 353 int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
 354 {
 355         u32 reg;
 356         struct exynos5_dp *base = dp->base;
 357
 358         reg = read32(&base->sys_ctl_1);
 359         write32(&base->sys_ctl_1, reg);
 360
 361         reg = read32(&base->sys_ctl_1);
 362
 363         if (!(reg & DET_STA))
 364                 return -1;
 365
 366         reg = read32(&base->sys_ctl_2);
 367         write32(&base->sys_ctl_2, reg);
 368
 369         reg = read32(&base->sys_ctl_2);
 370
 371         if (reg & CHA_STA) {
 372                 printk(BIOS_DEBUG, "Input stream clk is changing\n");
 373                 return -1;
 374         }
 375
 376         return 0;
 377 }
 378
 379 void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
 380                 enum clock_recovery_m_value_type type,
 381                 unsigned int m_value,
 382                 unsigned int n_value)
 383 {
 384         u32 reg;
 385         struct exynos5_dp *base = dp->base;
 386
 387         if (type == REGISTER_M) {
 388                 setbits32(&base->sys_ctl_4, FIX_M_VID);
 389
 390                 reg = m_value >> M_VID_0_VALUE_SHIFT;
 391                 write32(&base->m_vid_0, reg);
 392
 393                 reg = (m_value >> M_VID_1_VALUE_SHIFT);
 394                 write32(&base->m_vid_1, reg);
 395
 396                 reg = (m_value >> M_VID_2_VALUE_SHIFT);
 397                 write32(&base->m_vid_2, reg);
 398
 399                 reg = n_value >> N_VID_0_VALUE_SHIFT;
 400                 write32(&base->n_vid_0, reg);
 401
 402                 reg = (n_value >> N_VID_1_VALUE_SHIFT);
 403                 write32(&base->n_vid_1, reg);
 404
 405                 reg = (n_value >> N_VID_2_VALUE_SHIFT);
 406                 write32(&base->n_vid_2, reg);
 407         } else  {
 408                 clrbits32(&base->sys_ctl_4, FIX_M_VID);
 409
 410                 write32(&base->n_vid_0, 0x00);
 411                 write32(&base->n_vid_1, 0x80);
 412                 write32(&base->n_vid_2, 0x00);
 413         }
 414 }
 415
 416 void s5p_dp_enable_video_master(struct s5p_dp_device *dp)
 417 {
 418         u32 reg;
 419         struct exynos5_dp *base = dp->base;
 420
 421         reg = read32(&base->soc_general_ctl);
 422         reg &= ~VIDEO_MODE_MASK;
 423         reg |= VIDEO_MODE_SLAVE_MODE;
 424         write32(&base->soc_general_ctl, reg);
 425 }
 426
 427 int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
 428 {
 429         u32 reg, i = 0;
 430         struct stopwatch sw;
 431         struct exynos5_dp *base = dp->base;
 432
 433         /* Wait for 4 VSYNC_DET interrupts */
 434         stopwatch_init_msecs_expire(&sw, STREAM_ON_TIMEOUT);
 435
 436         do {
 437                 reg = read32(&base->common_int_sta_1);
 438                 if (reg & VSYNC_DET) {
 439                         i++;
 440                         write32(&base->common_int_sta_1, reg | VSYNC_DET);
 441                 }
 442                 if (i == 4)
 443                         break;
 444         } while (!stopwatch_expired(&sw));
 445
 446         if (i != 4) {
 447                 printk(BIOS_DEBUG, "s5p_dp_is_video_stream_on timeout\n");
 448                 return -1;
 449         }
 450
 451         return 0;
 452 }
 453
 454 void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
 455                         struct video_info *video_info)
 456 {
 457         u32 reg;
 458         struct exynos5_dp *base = dp->base;
 459
 460         reg = read32(&base->func_en_1);
 461         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
 462         reg |= MASTER_VID_FUNC_EN_N;
 463         write32(&base->func_en_1, reg);
 464
 465         reg = read32(&base->video_ctl_10);
 466         reg &= ~INTERACE_SCAN_CFG;
 467         reg |= (video_info->interlaced << 2);
 468         write32(&base->video_ctl_10, reg);
 469
 470         reg = read32(&base->video_ctl_10);
 471         reg &= ~VSYNC_POLARITY_CFG;
 472         reg |= (video_info->v_sync_polarity << 1);
 473         write32(&base->video_ctl_10, reg);
 474
 475         reg = read32(&base->video_ctl_10);
 476         reg &= ~HSYNC_POLARITY_CFG;
 477         reg |= (video_info->h_sync_polarity << 0);
 478         write32(&base->video_ctl_10, reg);
 479
 480         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
 481         write32(&base->soc_general_ctl, reg);
 482 }
 483
 484 void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
 485 {
 486         u32 reg;
 487         struct exynos5_dp *base = dp->base;
 488
 489         reg = read32(&base->dp_hw_link_training);
 490         while (reg & HW_TRAINING_EN)
 491                 reg = read32(&base->dp_hw_link_training);
 492 }