src/soc/rockchip/rk3399/usb.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <device/mmio.h>
  16 #include <assert.h>
  17 #include <console/console.h>
  18 #include <soc/clock.h>
  19 #include <soc/grf.h>
  20 #include <soc/soc.h>
  21 #include <soc/usb.h>
  22
  23 /* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just
  24  * gate off the SuperSpeed lines to have an unimpaired USB 2.0 connection. */
  25 static void isolate_tcphy(struct rk3399_tcphy *tcphy)
  26 {
  27         write32(&tcphy->isolation_ctrl,
  28                 TCPHY_ISOLATION_CTRL_EN |
  29                 TCPHY_ISOLATION_CTRL_CMN_EN |
  30                 TCPHY_ISOLATION_CTRL_MODE_SEL |
  31                 TCPHY_ISOLATION_CTRL_LN_EN(7) |
  32                 TCPHY_ISOLATION_CTRL_LN_EN(6) |
  33                 TCPHY_ISOLATION_CTRL_LN_EN(5) |
  34                 TCPHY_ISOLATION_CTRL_LN_EN(4) |
  35                 TCPHY_ISOLATION_CTRL_LN_EN(3) |
  36                 TCPHY_ISOLATION_CTRL_LN_EN(2) |
  37                 TCPHY_ISOLATION_CTRL_LN_EN(1) |
  38                 TCPHY_ISOLATION_CTRL_LN_EN(0));
  39 }
  40
  41 static void tcphy_cfg_24m(struct rk3399_tcphy *tcphy)
  42 {
  43         u32 i;
  44
  45         /* cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
  46          * cmn_psm_clk_dig_div = 2, set the clk division to 2 */
  47         write32(&tcphy->pma_cmn_ctrl1, 2 << 10 | 3 << 4);
  48         for (i = 0; i < 4; i++) {
  49                 /* The following PHY configuration assumes a
  50                  * 24 MHz reference clock */
  51                 write32(&tcphy->lane[i].xcvr_diag_lane_fcm_en_mgn, 0x90);
  52                 write32(&tcphy->lane[i].tx_rcvdet_en_tmr, 0x960);
  53                 write32(&tcphy->lane[i].tx_rcvdet_st_tmr, 0x30);
  54         }
  55
  56         clrsetbits32(&tcphy->cmn_diag_hsclk_sel,
  57                      TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG);
  58 }
  59
  60 static void tcphy_phy_init(struct rk3399_tcphy *tcphy)
  61 {
  62         u32 i;
  63
  64         tcphy_cfg_24m(tcphy);
  65
  66         for (i = 0; i < 4; i++) {
  67                 /* Enable transmitter reset pull down override for all lanes*/
  68                 write32(&tcphy->lane[i].tx_diag_tx_drv, 0x2000);
  69                 /* Disable transmitter low current mode, disable TX
  70                  * driver common mode, disable TX post-emphasis*/
  71                 write32(&tcphy->lane[i].tx_psc_a2, 0x0000);
  72         }
  73
  74         isolate_tcphy(tcphy);
  75 }
  76
  77 static void reset_dwc3(struct rockchip_usb_dwc3 *dwc3)
  78 {
  79         /* Before Resetting PHY, put Core in Reset */
  80         setbits32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET);
  81         /* Assert USB3 PHY reset */
  82         setbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST);
  83         /* Assert USB2 PHY reset */
  84         setbits32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  85 }
  86
  87 static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3)
  88 {
  89         u32 usb2phycfg = read32(&dwc3->usb2phycfg);
  90         u32 ctl = read32(&dwc3->ctl);
  91
  92         /* Ensure reset_dwc3() has been called before this. */
  93         assert(ctl & DWC3_GCTL_CORESOFTRESET);
  94
  95         /* Clear USB3 PHY reset (oddly enough, this is really necessary). */
  96         clrbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST);
  97
  98         /* Clear USB2 PHY and core reset. */
  99         usb2phycfg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 100         ctl &= ~DWC3_GCTL_CORESOFTRESET;
 101
 102         /* We are hard-coding DWC3 core to Host Mode */
 103         ctl &= ~DWC3_GCTL_PRTCAP_MASK;
 104         ctl |= DWC3_GCTL_PRTCAP_HOST;
 105
 106         /*
 107          * Configure USB phy interface of DWC3 core.
 108          * For Rockchip rk3399 SOC DWC3 core:
 109          * 1. Clear U2_FREECLK_EXITS.
 110          * 2. Select UTMI+ PHY with 16-bit interface.
 111          * 3. Set USBTRDTIM to the corresponding value
 112          * according to the UTMI+ PHY interface.
 113          */
 114         usb2phycfg &= ~(DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS |
 115                         DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
 116                         DWC3_GUSB2PHYCFG_PHYIF_MASK);
 117         usb2phycfg |= DWC3_GUSB2PHYCFG_PHYIF(1) |
 118                       DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 119
 120         write32(&dwc3->usb2phycfg, usb2phycfg);
 121         write32(&dwc3->ctl, ctl);
 122 }
 123
 124 void reset_usb_otg0(void)
 125 {
 126         printk(BIOS_DEBUG, "Starting DWC3 and TCPHY reset for USB OTG0\n");
 127
 128         /* Keep whole USB OTG0 controller in reset, then
 129          * configure controller to work in USB 2.0 only mode. */
 130         write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5));
 131         write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
 132         write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5));
 133
 134         tcphy_phy_init(rockchip_usb_otg0_phy);
 135
 136         /* Clear TCPHY0 reset */
 137         write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 5));
 138
 139         reset_dwc3(rockchip_usb_otg0_dwc3);
 140 }
 141
 142 void reset_usb_otg1(void)
 143 {
 144         printk(BIOS_DEBUG, "Starting DWC3 and TCPHY reset for USB OTG1\n");
 145
 146         /* Keep whole USB OTG1 controller in reset, then
 147          * configure controller to work in USB 2.0 only mode. */
 148         write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6));
 149         write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
 150         write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6));
 151
 152         tcphy_phy_init(rockchip_usb_otg1_phy);
 153
 154         /* Clear TCPHY1 reset */
 155         write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 13));
 156
 157         reset_dwc3(rockchip_usb_otg1_dwc3);
 158 }
 159
 160 void setup_usb_otg0(void)
 161 {
 162         /* Clear pipe reset */
 163         write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 4));
 164
 165         setup_dwc3(rockchip_usb_otg0_dwc3);
 166         printk(BIOS_DEBUG, "DWC3 and TCPHY setup for USB OTG0 finished\n");
 167 }
 168
 169 void setup_usb_otg1(void)
 170 {
 171         /* Clear pipe reset */
 172         write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 12));
 173
 174         setup_dwc3(rockchip_usb_otg1_dwc3);
 175         printk(BIOS_DEBUG, "DWC3 and TCPHY setup for USB OTG1 finished\n");
 176 }