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soc: Remove copyright notices
[coreboot.git] / src / soc / rockchip / rk3399 / clock.c
blobee04d5637d50214963b62b7ca7eebb2164d2515f
1 /*
2 * This file is part of the coreboot project.
3 *
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <assert.h>
16 #include <console/console.h>
17 #include <device/mmio.h>
18 #include <delay.h>
19 #include <soc/addressmap.h>
20 #include <soc/clock.h>
21 #include <soc/grf.h>
22 #include <soc/i2c.h>
23 #include <soc/soc.h>
24 #include <stdint.h>
25 #include <string.h>
26
27 struct pll_div {
28 u32 refdiv;
29 u32 fbdiv;
30 u32 postdiv1;
31 u32 postdiv2;
32 u32 frac;
33 u32 freq;
34 };
35
36 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
37 .refdiv = _refdiv,\
38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\
40 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
41 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
42 STRINGIFY(hz) " Hz cannot be hit with PLL "\
43 "divisors on line " STRINGIFY(__LINE__))
44
45 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
46 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1);
47 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1);
48
49 static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1);
50 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1);
51
52 static const struct pll_div *apll_cfgs[] = {
53 [APLL_1512_MHZ] = &apll_1512_cfg,
54 [APLL_600_MHZ] = &apll_600_cfg,
55 };
56
57 enum {
58 /* PLL_CON0 */
59 PLL_FBDIV_MASK = 0xfff,
60 PLL_FBDIV_SHIFT = 0,
61
62 /* PLL_CON1 */
63 PLL_POSTDIV2_MASK = 0x7,
64 PLL_POSTDIV2_SHIFT = 12,
65 PLL_POSTDIV1_MASK = 0x7,
66 PLL_POSTDIV1_SHIFT = 8,
67 PLL_REFDIV_MASK = 0x3f,
68 PLL_REFDIV_SHIFT = 0,
69
70 /* PLL_CON2 */
71 PLL_LOCK_STATUS_MASK = 1,
72 PLL_LOCK_STATUS_SHIFT = 31,
73 PLL_FRACDIV_MASK = 0xffffff,
74 PLL_FRACDIV_SHIFT = 0,
75
76 /* PLL_CON3 */
77 PLL_MODE_MASK = 3,
78 PLL_MODE_SHIFT = 8,
79 PLL_MODE_SLOW = 0,
80 PLL_MODE_NORM,
81 PLL_MODE_DEEP,
82 PLL_DSMPD_MASK = 1,
83 PLL_DSMPD_SHIFT = 3,
84 PLL_FRAC_MODE = 0,
85 PLL_INTEGER_MODE = 1,
86
87 /* PLL_CON4 */
88 PLL_SSMOD_BP_MASK = 1,
89 PLL_SSMOD_BP_SHIFT = 0,
90 PLL_SSMOD_DIS_SSCG_MASK = 1,
91 PLL_SSMOD_DIS_SSCG_SHIFT = 1,
92 PLL_SSMOD_RESET_MASK = 1,
93 PLL_SSMOD_RESET_SHIFT = 2,
94 PLL_SSMOD_DOWNSPEAD_MASK = 1,
95 PLL_SSMOD_DOWNSPEAD_SHIFT = 3,
96 PLL_SSMOD_DIVVAL_MASK = 0Xf,
97 PLL_SSMOD_DIVVAL_SHIFT = 4,
98 PLL_SSMOD_SPREADAMP_MASK = 0x1f,
99 PLL_SSMOD_SPREADAMP_SHIFT = 8,
100
101 /* PMUCRU_CLKSEL_CON0 */
102 PMU_PCLK_DIV_CON_MASK = 0x1f,
103 PMU_PCLK_DIV_CON_SHIFT = 0,
104
105 /* PMUCRU_CLKSEL_CON1 */
106 SPI3_PLL_SEL_MASK = 1,
107 SPI3_PLL_SEL_SHIFT = 7,
108 SPI3_PLL_SEL_24M = 0,
109 SPI3_PLL_SEL_PPLL = 1,
110 SPI3_DIV_CON_MASK = 0x7f,
111 SPI3_DIV_CON_SHIFT = 0x0,
112
113 /* PMUCRU_CLKSEL_CON2 */
114 I2C_DIV_CON_MASK = 0x7f,
115 I2C8_DIV_CON_SHIFT = 8,
116 I2C0_DIV_CON_SHIFT = 0,
117
118 /* PMUCRU_CLKSEL_CON3 */
119 I2C4_DIV_CON_SHIFT = 0,
120
121 /* CLKSEL_CON0 / CLKSEL_CON2 */
122 ACLKM_CORE_DIV_CON_MASK = 0x1f,
123 ACLKM_CORE_DIV_CON_SHIFT = 8,
124 CLK_CORE_PLL_SEL_MASK = 3,
125 CLK_CORE_PLL_SEL_SHIFT = 6,
126 CLK_CORE_PLL_SEL_ALPLL = 0x0,
127 CLK_CORE_PLL_SEL_ABPLL = 0x1,
128 CLK_CORE_PLL_SEL_DPLL = 0x10,
129 CLK_CORE_PLL_SEL_GPLL = 0x11,
130 CLK_CORE_DIV_MASK = 0x1f,
131 CLK_CORE_DIV_SHIFT = 0,
132
133 /* CLKSEL_CON1 / CLKSEL_CON3 */
134 PCLK_DBG_DIV_MASK = 0x1f,
135 PCLK_DBG_DIV_SHIFT = 0x8,
136 ATCLK_CORE_DIV_MASK = 0x1f,
137 ATCLK_CORE_DIV_SHIFT = 0,
138
139 /* CLKSEL_CON14 */
140 PCLK_PERIHP_DIV_CON_MASK = 0x7,
141 PCLK_PERIHP_DIV_CON_SHIFT = 12,
142 HCLK_PERIHP_DIV_CON_MASK = 3,
143 HCLK_PERIHP_DIV_CON_SHIFT = 8,
144 ACLK_PERIHP_PLL_SEL_MASK = 1,
145 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
146 ACLK_PERIHP_PLL_SEL_CPLL = 0,
147 ACLK_PERIHP_PLL_SEL_GPLL = 1,
148 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
149 ACLK_PERIHP_DIV_CON_SHIFT = 0,
150
151 /* CLKSEL_CON21 */
152 ACLK_EMMC_PLL_SEL_MASK = 0x1,
153 ACLK_EMMC_PLL_SEL_SHIFT = 7,
154 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
155 ACLK_EMMC_DIV_CON_MASK = 0x1f,
156 ACLK_EMMC_DIV_CON_SHIFT = 0,
157
158 /* CLKSEL_CON22 */
159 CLK_EMMC_PLL_MASK = 0x7,
160 CLK_EMMC_PLL_SHIFT = 8,
161 CLK_EMMC_PLL_SEL_GPLL = 0x1,
162 CLK_EMMC_DIV_CON_MASK = 0x7f,
163 CLK_EMMC_DIV_CON_SHIFT = 0,
164
165 /* CLKSEL_CON23 */
166 PCLK_PERILP0_DIV_CON_MASK = 0x7,
167 PCLK_PERILP0_DIV_CON_SHIFT = 12,
168 HCLK_PERILP0_DIV_CON_MASK = 3,
169 HCLK_PERILP0_DIV_CON_SHIFT = 8,
170 ACLK_PERILP0_PLL_SEL_MASK = 1,
171 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
172 ACLK_PERILP0_PLL_SEL_CPLL = 0,
173 ACLK_PERILP0_PLL_SEL_GPLL = 1,
174 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
175 ACLK_PERILP0_DIV_CON_SHIFT = 0,
176
177 /* CLKSEL_CON25 */
178 PCLK_PERILP1_DIV_CON_MASK = 0x7,
179 PCLK_PERILP1_DIV_CON_SHIFT = 8,
180 HCLK_PERILP1_PLL_SEL_MASK = 1,
181 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
182 HCLK_PERILP1_PLL_SEL_CPLL = 0,
183 HCLK_PERILP1_PLL_SEL_GPLL = 1,
184 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
185 HCLK_PERILP1_DIV_CON_SHIFT = 0,
186
187 /* CLKSEL_CON26 */
188 CLK_SARADC_DIV_CON_MASK = 0xff,
189 CLK_SARADC_DIV_CON_SHIFT = 8,
190
191 /* CLKSEL_CON27 */
192 CLK_TSADC_SEL_X24M = 0x0,
193 CLK_TSADC_SEL_MASK = 1,
194 CLK_TSADC_SEL_SHIFT = 15,
195 CLK_TSADC_DIV_CON_MASK = 0x3ff,
196 CLK_TSADC_DIV_CON_SHIFT = 0,
197
198 /* CLKSEL_CON44 */
199 CLK_PCLK_EDP_PLL_SEL_MASK = 1,
200 CLK_PCLK_EDP_PLL_SEL_SHIFT = 15,
201 CLK_PCLK_EDP_PLL_SEL_CPLL = 0,
202 CLK_PCLK_EDP_DIV_CON_MASK = 0x3f,
203 CLK_PCLK_EDP_DIV_CON_SHIFT = 8,
204
205 /* CLKSEL_CON47 & CLKSEL_CON48 */
206 ACLK_VOP_PLL_SEL_MASK = 0x3,
207 ACLK_VOP_PLL_SEL_SHIFT = 6,
208 ACLK_VOP_PLL_SEL_CPLL = 0x1,
209 ACLK_VOP_DIV_CON_MASK = 0x1f,
210 ACLK_VOP_DIV_CON_SHIFT = 0,
211
212 /* CLKSEL_CON49 & CLKSEL_CON50 */
213 DCLK_VOP_DCLK_SEL_MASK = 1,
214 DCLK_VOP_DCLK_SEL_SHIFT = 11,
215 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
216 DCLK_VOP_PLL_SEL_MASK = 3,
217 DCLK_VOP_PLL_SEL_SHIFT = 8,
218 DCLK_VOP_PLL_SEL_VPLL = 0,
219 DCLK_VOP_DIV_CON_MASK = 0xff,
220 DCLK_VOP_DIV_CON_SHIFT = 0,
221
222 /* CLKSEL_CON58 */
223 CLK_SPI_PLL_SEL_MASK = 1,
224 CLK_SPI_PLL_SEL_CPLL = 0,
225 CLK_SPI_PLL_SEL_GPLL = 1,
226 CLK_SPI_PLL_DIV_CON_MASK = 0x7f,
227 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
228 CLK_SPI5_PLL_SEL_SHIFT = 15,
229
230 /* CLKSEL_CON59 */
231 CLK_SPI1_PLL_SEL_SHIFT = 15,
232 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
233 CLK_SPI0_PLL_SEL_SHIFT = 7,
234 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
235
236 /* CLKSEL_CON60 */
237 CLK_SPI4_PLL_SEL_SHIFT = 15,
238 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
239 CLK_SPI2_PLL_SEL_SHIFT = 7,
240 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
241
242 /* CLKSEL_CON61 */
243 CLK_I2C_PLL_SEL_MASK = 1,
244 CLK_I2C_PLL_SEL_CPLL = 0,
245 CLK_I2C_PLL_SEL_GPLL = 1,
246 CLK_I2C5_PLL_SEL_SHIFT = 15,
247 CLK_I2C5_DIV_CON_SHIFT = 8,
248 CLK_I2C1_PLL_SEL_SHIFT = 7,
249 CLK_I2C1_DIV_CON_SHIFT = 0,
250
251 /* CLKSEL_CON62 */
252 CLK_I2C6_PLL_SEL_SHIFT = 15,
253 CLK_I2C6_DIV_CON_SHIFT = 8,
254 CLK_I2C2_PLL_SEL_SHIFT = 7,
255 CLK_I2C2_DIV_CON_SHIFT = 0,
256
257 /* CLKSEL_CON63 */
258 CLK_I2C7_PLL_SEL_SHIFT = 15,
259 CLK_I2C7_DIV_CON_SHIFT = 8,
260 CLK_I2C3_PLL_SEL_SHIFT = 7,
261 CLK_I2C3_DIV_CON_SHIFT = 0,
262
263 /* CRU_SOFTRST_CON4 */
264 RESETN_DDR0_REQ_MASK = 1,
265 RESETN_DDR0_REQ_SHIFT = 8,
266 RESETN_DDRPHY0_REQ_MASK = 1,
267 RESETN_DDRPHY0_REQ_SHIFT = 9,
268 RESETN_DDR1_REQ_MASK = 1,
269 RESETN_DDR1_REQ_SHIFT = 12,
270 RESETN_DDRPHY1_REQ_MASK = 1,
271 RESETN_DDRPHY1_REQ_SHIFT = 13,
272 };
273
274 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
275 #define VCO_MIN_KHZ (800 * (MHz / KHz))
276 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
277 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
278
279 /* the div restrictions of pll in integer mode,
280 * these are defined in * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
281 */
282 #define PLL_DIV_MIN 16
283 #define PLL_DIV_MAX 3200
284
285 /* How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
286 * Formulas also embedded within the Fractional PLL Verilog model:
287 * If DSMPD = 1 (DSM is disabled, "integer mode")
288 * FOUTVCO = FREF / REFDIV * FBDIV
289 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
290 * Where:
291 * FOUTVCO = Fractional PLL non-divided output frequency
292 * FOUTPOSTDIV = Fractional PLL divided output frequency
293 * (output of second post divider)
294 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
295 * REFDIV = Fractional PLL input reference clock divider
296 * FBDIV = Integer value programmed into feedback divide
297 *
298 */
299 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
300 {
301 /* All 8 PLLs have same VCO and output frequency range restrictions. */
302 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
303 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
304
305 printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
306 "postdiv2=%d, vco=%u kHz, output=%u kHz\n",
307 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
308 div->postdiv2, vco_khz, output_khz);
309 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
310 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
311 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
312
313 /* When power on or changing PLL setting,
314 * we must force PLL into slow mode to ensure output stable clock.
315 */
316 write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT,
317 PLL_MODE_SLOW << PLL_MODE_SHIFT));
318
319 /* use integer mode */
320 write32(&pll_con[3],
321 RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT,
322 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT));
323
324 write32(&pll_con[0], RK_CLRSETBITS(PLL_FBDIV_MASK << PLL_FBDIV_SHIFT,
325 div->fbdiv << PLL_FBDIV_SHIFT));
326 write32(&pll_con[1],
327 RK_CLRSETBITS(PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
328 PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT |
329 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
330 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
331 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
332 (div->refdiv << PLL_REFDIV_SHIFT)));
333
334 /* waiting for pll lock */
335 while (!(read32(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
336 udelay(1);
337
338 /* pll enter normal mode */
339 write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT,
340 PLL_MODE_NORM << PLL_MODE_SHIFT));
341 }
342
343 /*
344 * Configure the DPLL spread spectrum feature on memory clock.
345 * Configure sequence:
346 * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0.
347 * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with
348 * extern wave table).
349 * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0.
350 * 4. Assert RESET = 1'b1 to SSMOD.
351 * 5. RESET = 1'b0 on SSMOD.
352 * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD.
353 */
354 static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
355 {
356 u32 divval;
357
358 assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);
359
360 /*
361 * Need to acquire ~30kHZ which is the target modulation frequency.
362 * The modulation frequency ~ 30kHz= OSC_HZ/revdiv/128/divval
363 * (the 128 is the number points in the query table).
364 */
365 divval = OSC_HZ / 128 / (30 * KHz) / dpll_cfg->refdiv;
366
367 /*
368 * Use frac mode.
369 * Make sure the output frequency isn't offset, set 0 for Fractional
370 * part of feedback divide.
371 */
372 write32(&cru_ptr->dpll_con[3],
373 RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT,
374 PLL_FRAC_MODE << PLL_DSMPD_SHIFT));
375 clrsetbits32(&cru_ptr->dpll_con[2],
376 PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT,
377 0 << PLL_FRACDIV_SHIFT);
378
379 /*
380 * Configure SSC divval.
381 * Spread amplitude range = 0.1 * SPREAD[4:0] (%).
382 * The below 8 means SPREAD[4:0] that appears to mitigate EMI on boards
383 * tested. Center and down spread modulation amplitudes based on the
384 * value of SPREAD.
385 * SPREAD[4:0] Center Spread Down Spread
386 * 0 0 0
387 * 1 +/-0.1% -0.10%
388 * 2 +/-0.2% -0.20%
389 * 3 +/-0.3% -0.30%
390 * 4 +/-0.4% -0.40%
391 * 5 +/-0.5% -0.50%
392 * ...
393 * 31 +/-3.1% -3.10%
394 */
395 write32(&cru_ptr->dpll_con[4],
396 RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT,
397 divval << PLL_SSMOD_DIVVAL_SHIFT));
398 write32(&cru_ptr->dpll_con[4],
399 RK_CLRSETBITS(PLL_SSMOD_SPREADAMP_MASK <<
400 PLL_SSMOD_SPREADAMP_SHIFT,
401 8 << PLL_SSMOD_SPREADAMP_SHIFT));
402
403 /* Enable SSC for DPLL */
404 write32(&cru_ptr->dpll_con[4],
405 RK_CLRBITS(PLL_SSMOD_BP_MASK << PLL_SSMOD_BP_SHIFT |
406 PLL_SSMOD_DIS_SSCG_MASK << PLL_SSMOD_DIS_SSCG_SHIFT));
407
408 /* Deassert reset SSMOD */
409 write32(&cru_ptr->dpll_con[4],
410 RK_CLRBITS(PLL_SSMOD_RESET_MASK << PLL_SSMOD_RESET_SHIFT));
411
412 udelay(20);
413 }
414
415 static int pll_para_config(u32 freq_hz, struct pll_div *div)
416 {
417 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
418 u32 postdiv1, postdiv2 = 1;
419 u32 fref_khz;
420 u32 diff_khz, best_diff_khz;
421 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
422 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
423 u32 vco_khz;
424 u32 freq_khz = freq_hz / KHz;
425
426 if (!freq_hz) {
427 printk(BIOS_ERR, "%s: the frequency can't be 0 Hz\n", __func__);
428 return -1;
429 }
430
431 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
432 if (postdiv1 > max_postdiv1) {
433 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
434 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
435 }
436
437 vco_khz = freq_khz * postdiv1 * postdiv2;
438
439 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
440 postdiv2 > max_postdiv2) {
441 printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
442 " for Frequency (%uHz).\n", __func__, freq_hz);
443 return -1;
444 }
445
446 div->postdiv1 = postdiv1;
447 div->postdiv2 = postdiv2;
448
449 best_diff_khz = vco_khz;
450 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
451 fref_khz = ref_khz / refdiv;
452
453 fbdiv = vco_khz / fref_khz;
454 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
455 continue;
456 diff_khz = vco_khz - fbdiv * fref_khz;
457 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
458 fbdiv++;
459 diff_khz = fref_khz - diff_khz;
460 }
461
462 if (diff_khz >= best_diff_khz)
463 continue;
464
465 best_diff_khz = diff_khz;
466 div->refdiv = refdiv;
467 div->fbdiv = fbdiv;
468 }
469
470 if (best_diff_khz > 4 * (MHz/KHz)) {
471 printk(BIOS_ERR, "%s: Failed to match output frequency %u, "
472 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
473 best_diff_khz * KHz);
474 return -1;
475 }
476 return 0;
477 }
478
479 void rkclk_init(void)
480 {
481 u32 aclk_div;
482 u32 hclk_div;
483 u32 pclk_div;
484
485 /* some cru registers changed by bootrom, we'd better reset them to
486 * reset/default values described in TRM to avoid confusion in kernel.
487 * Please consider these three lines as a fix of bootrom bug.
488 */
489 write32(&cru_ptr->clksel_con[12], 0xffff4101);
490 write32(&cru_ptr->clksel_con[19], 0xffff033f);
491 write32(&cru_ptr->clksel_con[56], 0x00030003);
492
493 /* configure pmu pll(ppll) */
494 rkclk_set_pll(&pmucru_ptr->ppll_con[0], &ppll_init_cfg);
495
496 /* configure pmu pclk */
497 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
498 assert((unsigned int)(PPLL_HZ - (pclk_div + 1) * PMU_PCLK_HZ) <= pclk_div
499 && pclk_div <= 0x1f);
500 write32(&pmucru_ptr->pmucru_clksel[0],
501 RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT,
502 pclk_div << PMU_PCLK_DIV_CON_SHIFT));
503
504 /* configure gpll cpll */
505 rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg);
506 rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg);
507
508 /* configure perihp aclk, hclk, pclk */
509 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
510 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
511
512 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
513 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
514 PERIHP_ACLK_HZ && (hclk_div <= 0x3));
515
516 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
517 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
518 PERIHP_ACLK_HZ && (pclk_div <= 0x7));
519
520 write32(&cru_ptr->clksel_con[14],
521 RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK <<
522 PCLK_PERIHP_DIV_CON_SHIFT |
523 HCLK_PERIHP_DIV_CON_MASK <<
524 HCLK_PERIHP_DIV_CON_SHIFT |
525 ACLK_PERIHP_PLL_SEL_MASK <<
526 ACLK_PERIHP_PLL_SEL_SHIFT |
527 ACLK_PERIHP_DIV_CON_MASK <<
528 ACLK_PERIHP_DIV_CON_SHIFT,
529 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
530 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
531 ACLK_PERIHP_PLL_SEL_GPLL <<
532 ACLK_PERIHP_PLL_SEL_SHIFT |
533 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT));
534
535 /* configure perilp0 aclk, hclk, pclk */
536 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
537 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
538
539 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
540 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
541 PERILP0_ACLK_HZ && (hclk_div <= 0x3));
542
543 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
544 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
545 PERILP0_ACLK_HZ && (pclk_div <= 0x7));
546
547 write32(&cru_ptr->clksel_con[23],
548 RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK <<
549 PCLK_PERILP0_DIV_CON_SHIFT |
550 HCLK_PERILP0_DIV_CON_MASK <<
551 HCLK_PERILP0_DIV_CON_SHIFT |
552 ACLK_PERILP0_PLL_SEL_MASK <<
553 ACLK_PERILP0_PLL_SEL_SHIFT |
554 ACLK_PERILP0_DIV_CON_MASK <<
555 ACLK_PERILP0_DIV_CON_SHIFT,
556 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
557 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
558 ACLK_PERILP0_PLL_SEL_GPLL <<
559 ACLK_PERILP0_PLL_SEL_SHIFT |
560 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT));
561
562 /* perilp1 hclk select gpll as source */
563 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
564 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
565 GPLL_HZ && (hclk_div <= 0x1f));
566
567 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1;
568 assert((pclk_div + 1) * PERILP1_PCLK_HZ ==
569 PERILP1_HCLK_HZ && (pclk_div <= 0x7));
570
571 write32(&cru_ptr->clksel_con[25],
572 RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK <<
573 PCLK_PERILP1_DIV_CON_SHIFT |
574 HCLK_PERILP1_DIV_CON_MASK <<
575 HCLK_PERILP1_DIV_CON_SHIFT |
576 HCLK_PERILP1_PLL_SEL_MASK <<
577 HCLK_PERILP1_PLL_SEL_SHIFT,
578 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
579 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
580 HCLK_PERILP1_PLL_SEL_GPLL <<
581 HCLK_PERILP1_PLL_SEL_SHIFT));
582 }
583
584 void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
585 {
586 u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz;
587 int con_base, parent;
588 u32 *pll_con;
589
590 switch (cluster) {
591 case CPU_CLUSTER_LITTLE:
592 con_base = 0;
593 parent = CLK_CORE_PLL_SEL_ALPLL;
594 pll_con = &cru_ptr->apll_l_con[0];
595 break;
596 case CPU_CLUSTER_BIG:
597 default:
598 con_base = 2;
599 parent = CLK_CORE_PLL_SEL_ABPLL;
600 pll_con = &cru_ptr->apll_b_con[0];
601 break;
602 }
603
604 apll_hz = apll_cfgs[freq]->freq;
605 rkclk_set_pll(pll_con, apll_cfgs[freq]);
606
607 aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1;
608 pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1;
609 atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1;
610
611 write32(&cru_ptr->clksel_con[con_base],
612 RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<
613 ACLKM_CORE_DIV_CON_SHIFT |
614 CLK_CORE_PLL_SEL_MASK << CLK_CORE_PLL_SEL_SHIFT |
615 CLK_CORE_DIV_MASK << CLK_CORE_DIV_SHIFT,
616 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT |
617 parent << CLK_CORE_PLL_SEL_SHIFT |
618 0 << CLK_CORE_DIV_SHIFT));
619
620 write32(&cru_ptr->clksel_con[con_base + 1],
621 RK_CLRSETBITS(PCLK_DBG_DIV_MASK << PCLK_DBG_DIV_SHIFT |
622 ATCLK_CORE_DIV_MASK << ATCLK_CORE_DIV_SHIFT,
623 pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
624 atclk_div << ATCLK_CORE_DIV_SHIFT));
625 }
626
627 void rkclk_configure_ddr(unsigned int hz)
628 {
629 struct pll_div dpll_cfg;
630
631 /* IC ECO bug, need to set this register */
632 write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000);
633
634 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
635 switch (hz) {
636 case 200*MHz:
637 dpll_cfg = (struct pll_div)
638 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2};
639 break;
640 case 300*MHz:
641 dpll_cfg = (struct pll_div)
642 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
643 break;
644 case 666*MHz:
645 dpll_cfg = (struct pll_div)
646 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
647 break;
648 case 800*MHz:
649 dpll_cfg = (struct pll_div)
650 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
651 break;
652 case 933*MHz:
653 dpll_cfg = (struct pll_div)
654 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
655 break;
656 default:
657 die("Unsupported SDRAM frequency, add to clock.c!");
658 }
659 rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg);
660
661 if (CONFIG(RK3399_SPREAD_SPECTRUM_DDR))
662 rkclk_set_dpllssc(&dpll_cfg);
663 }
664
665 #define SPI_CLK_REG_VALUE(bus, clk_div) \
666 RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \
667 CLK_SPI ##bus## _PLL_SEL_SHIFT | \
668 CLK_SPI_PLL_DIV_CON_MASK << \
669 CLK_SPI ##bus## _PLL_DIV_CON_SHIFT, \
670 CLK_SPI_PLL_SEL_GPLL << \
671 CLK_SPI ##bus## _PLL_SEL_SHIFT | \
672 (clk_div - 1) << \
673 CLK_SPI ##bus## _PLL_DIV_CON_SHIFT)
674
675 void rkclk_configure_spi(unsigned int bus, unsigned int hz)
676 {
677 int src_clk_div;
678 int pll;
679
680 /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */
681 pll = (bus == 3) ? PPLL_HZ : GPLL_HZ;
682 src_clk_div = pll / hz;
683 assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll));
684
685 switch (bus) {
686 case 0:
687 write32(&cru_ptr->clksel_con[59],
688 SPI_CLK_REG_VALUE(0, src_clk_div));
689 break;
690 case 1:
691 write32(&cru_ptr->clksel_con[59],
692 SPI_CLK_REG_VALUE(1, src_clk_div));
693 break;
694 case 2:
695 write32(&cru_ptr->clksel_con[60],
696 SPI_CLK_REG_VALUE(2, src_clk_div));
697 break;
698 case 3:
699 write32(&pmucru_ptr->pmucru_clksel[1],
700 RK_CLRSETBITS(SPI3_PLL_SEL_MASK << SPI3_PLL_SEL_SHIFT |
701 SPI3_DIV_CON_MASK << SPI3_DIV_CON_SHIFT,
702 SPI3_PLL_SEL_PPLL << SPI3_PLL_SEL_SHIFT |
703 (src_clk_div - 1) << SPI3_DIV_CON_SHIFT));
704 break;
705 case 4:
706 write32(&cru_ptr->clksel_con[60],
707 SPI_CLK_REG_VALUE(4, src_clk_div));
708 break;
709 case 5:
710 write32(&cru_ptr->clksel_con[58],
711 SPI_CLK_REG_VALUE(5, src_clk_div));
712 break;
713 default:
714 printk(BIOS_ERR, "do not support this spi bus\n");
715 }
716 }
717
718 #define I2C_CLK_REG_VALUE(bus, clk_div) \
719 RK_CLRSETBITS(I2C_DIV_CON_MASK << \
720 CLK_I2C ##bus## _DIV_CON_SHIFT | \
721 CLK_I2C_PLL_SEL_MASK << \
722 CLK_I2C ##bus## _PLL_SEL_SHIFT, \
723 (clk_div - 1) << \
724 CLK_I2C ##bus## _DIV_CON_SHIFT | \
725 CLK_I2C_PLL_SEL_GPLL << \
726 CLK_I2C ##bus## _PLL_SEL_SHIFT)
727 #define PMU_I2C_CLK_REG_VALUE(bus, clk_div) \
728 RK_CLRSETBITS(I2C_DIV_CON_MASK << I2C ##bus## _DIV_CON_SHIFT, \
729 (clk_div - 1) << I2C ##bus## _DIV_CON_SHIFT)
730
731 uint32_t rkclk_i2c_clock_for_bus(unsigned int bus)
732 {
733 int src_clk_div, pll, freq;
734
735 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll */
736 if (bus == 0 || bus == 4 || bus == 8) {
737 pll = PPLL_HZ;
738 freq = 338*MHz;
739 } else {
740 pll = GPLL_HZ;
741 freq = 198*MHz;
742 }
743 src_clk_div = pll / freq;
744 assert((src_clk_div - 1 <= 127) && (src_clk_div * freq == pll));
745
746 switch (bus) {
747 case 0:
748 write32(&pmucru_ptr->pmucru_clksel[2],
749 PMU_I2C_CLK_REG_VALUE(0, src_clk_div));
750 break;
751 case 1:
752 write32(&cru_ptr->clksel_con[61],
753 I2C_CLK_REG_VALUE(1, src_clk_div));
754 break;
755 case 2:
756 write32(&cru_ptr->clksel_con[62],
757 I2C_CLK_REG_VALUE(2, src_clk_div));
758 break;
759 case 3:
760 write32(&cru_ptr->clksel_con[63],
761 I2C_CLK_REG_VALUE(3, src_clk_div));
762 break;
763 case 4:
764 write32(&pmucru_ptr->pmucru_clksel[3],
765 PMU_I2C_CLK_REG_VALUE(4, src_clk_div));
766 break;
767 case 5:
768 write32(&cru_ptr->clksel_con[61],
769 I2C_CLK_REG_VALUE(5, src_clk_div));
770 break;
771 case 6:
772 write32(&cru_ptr->clksel_con[62],
773 I2C_CLK_REG_VALUE(6, src_clk_div));
774 break;
775 case 7:
776 write32(&cru_ptr->clksel_con[63],
777 I2C_CLK_REG_VALUE(7, src_clk_div));
778 break;
779 case 8:
780 write32(&pmucru_ptr->pmucru_clksel[2],
781 PMU_I2C_CLK_REG_VALUE(8, src_clk_div));
782 break;
783 default:
784 die("unknown i2c bus\n");
785 }
786
787 return freq;
788 }
789
790 static u32 clk_gcd(u32 a, u32 b)
791 {
792 while (b != 0) {
793 int r = b;
794 b = a % b;
795 a = r;
796 }
797 return a;
798 }
799
800 void rkclk_configure_i2s(unsigned int hz)
801 {
802 int n, d;
803 int v;
804
805 /**
806 * clk_i2s0_sel: divider output from fraction
807 * clk_i2s0_pll_sel source clock: cpll
808 * clk_i2s0_div_con: 1 (div+1)
809 */
810 write32(&cru_ptr->clksel_con[28],
811 RK_CLRSETBITS(3 << 8 | 1 << 7 | 0x7f << 0,
812 1 << 8 | 0 << 7 | 0 << 0));
813
814 /* make sure and enable i2s0 path gates */
815 write32(&cru_ptr->clkgate_con[8],
816 RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3));
817
818 /* set frac divider */
819 v = clk_gcd(CPLL_HZ, hz);
820 n = (CPLL_HZ / v) & (0xffff);
821 d = (hz / v) & (0xffff);
822 assert(hz == (u64)CPLL_HZ * d / n);
823 write32(&cru_ptr->clksel_con[96], d << 16 | n);
824
825 /**
826 * clk_i2sout_sel clk_i2s
827 * clk_i2s_ch_sel: clk_i2s0
828 */
829 write32(&cru_ptr->clksel_con[31],
830 RK_CLRSETBITS(1 << 2 | 3 << 0,
831 0 << 2 | 0 << 0));
832 }
833
834 void rkclk_configure_saradc(unsigned int hz)
835 {
836 int src_clk_div;
837
838 /* saradc src clk from 24MHz */
839 src_clk_div = 24 * MHz / hz;
840 assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz));
841
842 write32(&cru_ptr->clksel_con[26],
843 RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK <<
844 CLK_SARADC_DIV_CON_SHIFT,
845 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT));
846 }
847
848 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
849 {
850 u32 div;
851 void *reg_addr = vop_id ? &cru_ptr->clksel_con[48] :
852 &cru_ptr->clksel_con[47];
853
854 /* vop aclk source clk: cpll */
855 div = CPLL_HZ / aclk_hz;
856 assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ));
857
858 write32(reg_addr, RK_CLRSETBITS(
859 ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT |
860 ACLK_VOP_DIV_CON_MASK << ACLK_VOP_DIV_CON_SHIFT,
861 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
862 (div - 1) << ACLK_VOP_DIV_CON_SHIFT));
863 }
864
865 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
866 {
867 struct pll_div vpll_config = {0};
868 void *reg_addr = vop_id ? &cru_ptr->clksel_con[50] :
869 &cru_ptr->clksel_con[49];
870
871 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
872 if (pll_para_config(dclk_hz, &vpll_config))
873 return -1;
874
875 rkclk_set_pll(&cru_ptr->vpll_con[0], &vpll_config);
876
877 write32(reg_addr, RK_CLRSETBITS(
878 DCLK_VOP_DCLK_SEL_MASK << DCLK_VOP_DCLK_SEL_SHIFT |
879 DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT |
880 DCLK_VOP_DIV_CON_MASK << DCLK_VOP_DIV_CON_SHIFT,
881 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
882 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
883 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT));
884
885 return 0;
886 }
887
888 void rkclk_configure_tsadc(unsigned int hz)
889 {
890 int src_clk_div;
891
892 /* use 24M as src clock */
893 src_clk_div = OSC_HZ / hz;
894 assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ));
895
896 write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS(
897 CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT |
898 CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT,
899 src_clk_div << CLK_TSADC_DIV_CON_SHIFT |
900 CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT));
901 }
902
903 void rkclk_configure_emmc(void)
904 {
905 int src_clk_div;
906 int aclk_emmc = 148500*KHz;
907 int clk_emmc = 148500*KHz;
908
909 /* Select aclk_emmc source from GPLL */
910 src_clk_div = GPLL_HZ / aclk_emmc;
911 assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ));
912
913 write32(&cru_ptr->clksel_con[21],
914 RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK <<
915 ACLK_EMMC_PLL_SEL_SHIFT |
916 ACLK_EMMC_DIV_CON_MASK << ACLK_EMMC_DIV_CON_SHIFT,
917 ACLK_EMMC_PLL_SEL_GPLL <<
918 ACLK_EMMC_PLL_SEL_SHIFT |
919 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT));
920
921 /* Select clk_emmc source from GPLL too */
922 src_clk_div = GPLL_HZ / clk_emmc;
923 assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ));
924
925 write32(&cru_ptr->clksel_con[22],
926 RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |
927 CLK_EMMC_DIV_CON_MASK << CLK_EMMC_DIV_CON_SHIFT,
928 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
929 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
930 }
931
932 int rkclk_was_watchdog_reset(void)
933 {
934 /* Bits 5 and 4 are "second" and "first" global watchdog reset. */
935 return read32(&cru_ptr->glb_rst_st) & 0x30;
936 }
937
938 void rkclk_configure_edp(unsigned int hz)
939 {
940 int src_clk_div;
941
942 src_clk_div = CPLL_HZ / hz;
943 assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ));
944
945 write32(&cru_ptr->clksel_con[44],
946 RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK <<
947 CLK_PCLK_EDP_PLL_SEL_SHIFT |
948 CLK_PCLK_EDP_DIV_CON_MASK <<
949 CLK_PCLK_EDP_DIV_CON_SHIFT,
950 CLK_PCLK_EDP_PLL_SEL_CPLL <<
951 CLK_PCLK_EDP_PLL_SEL_SHIFT |
952 (src_clk_div - 1) <<
953 CLK_PCLK_EDP_DIV_CON_SHIFT));
954 }
955
956 void rkclk_configure_mipi(void)
957 {
958 /* Enable clk_mipidphy_ref and clk_mipidphy_cfg */
959 write32(&cru_ptr->clkgate_con[11],
960 RK_CLRBITS(1 << 14 | 1 << 15));
961 /* Enable pclk_mipi_dsi0 */
962 write32(&cru_ptr->clkgate_con[29],
963 RK_CLRBITS(1 << 1));
964 }
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