src/soc/rockchip/rk3288/hdmi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /*
  17  * Designware High-Definition Multimedia Interface (HDMI) driveG
  18  */
  19
  20 #include <device/mmio.h>
  21 #include <console/console.h>
  22 #include <delay.h>
  23 #include <edid.h>
  24 #include <gpio.h>
  25 #include <stdint.h>
  26 #include <soc/addressmap.h>
  27 #include <soc/hdmi.h>
  28 #include <soc/grf.h>
  29 #include <soc/vop.h>
  30 #include <timer.h>
  31
  32 #include "chip.h"
  33
  34 #define AUDIO_SAMPLERATE_DEFAULT        (48*KHz)
  35
  36 #define hdmi_debug(x...)        do { if (0) printk(BIOS_DEBUG, x); } while (0)
  37
  38 struct rk3288_hdmi_regs * const hdmi_regs = (void *)HDMI_TX_BASE;
  39
  40 struct tmds_n_cts {
  41         u32 tmds;
  42         u32 cts;
  43         u32 n;
  44 };
  45
  46 static const struct tmds_n_cts n_cts_table[] = {
  47         {
  48                 .tmds = 25175, .n = 6144, .cts = 25175,
  49         }, {
  50                 .tmds = 25200, .n = 6144, .cts = 25200,
  51         }, {
  52                 .tmds = 27000, .n = 6144, .cts = 27000,
  53         }, {
  54                 .tmds = 27027, .n = 6144, .cts = 27027,
  55         }, {
  56                 .tmds = 40000, .n = 6144, .cts = 40000,
  57         }, {
  58                 .tmds = 54000, .n = 6144, .cts = 54000,
  59         }, {
  60                 .tmds = 54054, .n = 6144, .cts = 54054,
  61         }, {
  62                 .tmds = 65000, .n = 6144, .cts = 65000,
  63         }, {
  64                 .tmds = 74176, .n = 11648, .cts = 140625,
  65         }, {
  66                 .tmds = 74250, .n = 6144, .cts = 74250,
  67         }, {
  68                 .tmds = 83500, .n = 6144, .cts = 83500,
  69         }, {
  70                 .tmds = 106500, .n = 6144, .cts = 106500,
  71         }, {
  72                 .tmds = 108000, .n = 6144, .cts = 108000,
  73         }, {
  74                 .tmds = 148352, .n = 5824, .cts = 140625,
  75         }, {
  76                 .tmds = 148500, .n = 6144, .cts = 148500,
  77         }, {
  78                 .tmds = 297000, .n = 5120, .cts = 247500,
  79         }
  80 };
  81
  82 struct hdmi_mpll_config {
  83         u64 mpixelclock;
  84         /* Mode of Operation and PLL Dividers Control Register */
  85         u32 cpce;
  86         /* PLL Gmp Control Register */
  87         u32 gmp;
  88         /* PLL Current COntrol Register */
  89         u32 curr;
  90 };
  91
  92 struct hdmi_phy_config {
  93         u64 mpixelclock;
  94         u32 sym_ctr;    /* clock symbol and transmitter control */
  95         u32 term;       /* transmission termination value */
  96         u32 vlev_ctr;   /* voltage level control */
  97 };
  98
  99 static const struct hdmi_phy_config rockchip_phy_config[] = {
 100         {
 101                 .mpixelclock = 74250,
 102                 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
 103         }, {
 104                 .mpixelclock = 148500,
 105                 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
 106         }, {
 107                 .mpixelclock = 297000,
 108                 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
 109         }, {
 110                 .mpixelclock = ~0ul,
 111                 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
 112         }
 113 };
 114
 115 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
 116         {
 117                 .mpixelclock = 40000,
 118                 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
 119         }, {
 120                 .mpixelclock = 65000,
 121                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
 122         }, {
 123                 .mpixelclock = 66000,
 124                 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
 125         }, {
 126                 .mpixelclock = 83500,
 127                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
 128         }, {
 129                 .mpixelclock = 146250,
 130                 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
 131         }, {
 132                 .mpixelclock = 148500,
 133                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
 134         }, {
 135                 .mpixelclock = ~0ul,
 136                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
 137         }
 138 };
 139
 140 static const u32 csc_coeff_default[3][4] = {
 141         { 0x2000, 0x0000, 0x0000, 0x0000 },
 142         { 0x0000, 0x2000, 0x0000, 0x0000 },
 143         { 0x0000, 0x0000, 0x2000, 0x0000 }
 144 };
 145
 146 static void hdmi_set_clock_regenerator(u32 n, u32 cts)
 147 {
 148         u8 cts3;
 149         u8 n3;
 150
 151         /* first set ncts_atomic_write (if present) */
 152         n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
 153         write32(&hdmi_regs->aud_n3, n3);
 154
 155         /* set cts_manual (if present) */
 156         cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
 157
 158         cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
 159         cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
 160
 161         /* write cts values; cts3 must be written first */
 162         write32(&hdmi_regs->aud_cts3, cts3);
 163         write32(&hdmi_regs->aud_cts2, (cts >> 8) & 0xff);
 164         write32(&hdmi_regs->aud_cts1, cts & 0xff);
 165
 166         /* write n values; n1 must be written last */
 167         n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
 168         write32(&hdmi_regs->aud_n3, n3);
 169         write32(&hdmi_regs->aud_n2, (n >> 8) & 0xff);
 170         write32(&hdmi_regs->aud_n1, n & 0xff);
 171
 172         write32(&hdmi_regs->aud_inputclkfs, HDMI_AUD_INPUTCLKFS_128);
 173 }
 174
 175 static int hdmi_lookup_n_cts(u32 pixel_clk)
 176 {
 177         int i;
 178
 179         for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
 180                 if (pixel_clk <= n_cts_table[i].tmds)
 181                         break;
 182
 183         if (i >= ARRAY_SIZE(n_cts_table))
 184                 return -1;
 185
 186         return i;
 187 }
 188
 189 static void hdmi_audio_set_samplerate(u32 pixel_clk)
 190 {
 191         u32 clk_n, clk_cts;
 192         int index;
 193
 194         index = hdmi_lookup_n_cts(pixel_clk);
 195         if (index == -1) {
 196                 hdmi_debug("audio not supported for pixel clk %d\n", pixel_clk);
 197                 return;
 198         }
 199
 200         clk_n = n_cts_table[index].n;
 201         clk_cts = n_cts_table[index].cts;
 202         hdmi_set_clock_regenerator(clk_n, clk_cts);
 203 }
 204
 205 /*
 206  * this submodule is responsible for the video data synchronization.
 207  * for example, for rgb 4:4:4 input, the data map is defined as
 208  *                      pin{47~40} <==> r[7:0]
 209  *                      pin{31~24} <==> g[7:0]
 210  *                      pin{15~8}  <==> b[7:0]
 211  */
 212 static void hdmi_video_sample(void)
 213 {
 214         u32 color_format = 0x01;
 215         u8 val;
 216
 217         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 218               ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 219               HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 220
 221         write32(&hdmi_regs->tx_invid0, val);
 222
 223         /* enable tx stuffing: when de is inactive, fix the output data to 0 */
 224         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 225               HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 226               HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 227         write32(&hdmi_regs->tx_instuffing, val);
 228         write32(&hdmi_regs->tx_gydata0, 0x0);
 229         write32(&hdmi_regs->tx_gydata1, 0x0);
 230         write32(&hdmi_regs->tx_rcrdata0, 0x0);
 231         write32(&hdmi_regs->tx_rcrdata1, 0x0);
 232         write32(&hdmi_regs->tx_bcbdata0, 0x0);
 233         write32(&hdmi_regs->tx_bcbdata1, 0x0);
 234 }
 235
 236 static void hdmi_update_csc_coeffs(void)
 237 {
 238         u32 i, j;
 239         u32 csc_scale = 1;
 240
 241         /* the csc registers are sequential, alternating msb then lsb */
 242         for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) {
 243                 for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) {
 244                         u32 coeff = csc_coeff_default[i][j];
 245                         write32(&hdmi_regs->csc_coef[i][j].msb, coeff >> 8);
 246                         write32(&hdmi_regs->csc_coef[i][j].lsb, coeff & 0xff);
 247                 }
 248         }
 249
 250         clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 251                      csc_scale);
 252 }
 253
 254 static void hdmi_video_csc(void)
 255 {
 256         u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 257         u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 258
 259         /* configure the csc registers */
 260         write32(&hdmi_regs->csc_cfg, interpolation);
 261         clrsetbits32(&hdmi_regs->csc_scale,
 262                      HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth);
 263
 264         hdmi_update_csc_coeffs();
 265 }
 266
 267 static void hdmi_video_packetize(void)
 268 {
 269         u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 270         u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
 271         u32 color_depth = 0;
 272         u8 val, vp_conf;
 273
 274         /* set the packetizer registers */
 275         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 276                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 277                 ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 278                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 279         write32(&hdmi_regs->vp_pr_cd, val);
 280
 281         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
 282                      HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
 283
 284         /* data from pixel repeater block */
 285         vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 286                   HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 287
 288         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
 289                      HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
 290
 291         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
 292                      1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
 293
 294         write32(&hdmi_regs->vp_remap, remap_size);
 295
 296         vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 297                   HDMI_VP_CONF_PP_EN_DISABLE |
 298                   HDMI_VP_CONF_YCC422_EN_DISABLE;
 299
 300         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
 301                      HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
 302                      vp_conf);
 303
 304         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
 305                      HDMI_VP_STUFF_YCC422_STUFFING_MASK,
 306                      HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 307                      HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
 308
 309         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 310                      output_select);
 311 }
 312
 313 static inline void hdmi_phy_test_clear(u8 bit)
 314 {
 315         clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
 316                      bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
 317 }
 318
 319 static int hdmi_phy_wait_i2c_done(u32 msec)
 320 {
 321         struct stopwatch phyi2c_done;
 322         u32 val;
 323
 324         stopwatch_init_msecs_expire(&phyi2c_done, msec);
 325         do {
 326                 val = read32(&hdmi_regs->ih_i2cmphy_stat0);
 327                 if (val & 0x3) {
 328                         write32(&hdmi_regs->ih_i2cmphy_stat0, val);
 329                         return 0;
 330                 }
 331
 332                 udelay(100);
 333         } while (!stopwatch_expired(&phyi2c_done));
 334
 335         return 1;
 336 }
 337
 338 static void hdmi_phy_i2c_write(u16 data, u8 addr)
 339 {
 340         write32(&hdmi_regs->ih_i2cmphy_stat0, 0xff);
 341         write32(&hdmi_regs->phy_i2cm_address_addr, addr);
 342         write32(&hdmi_regs->phy_i2cm_datao_1_addr, (u8)(data >> 8));
 343         write32(&hdmi_regs->phy_i2cm_datao_0_addr, (u8)(data >> 0));
 344         write32(&hdmi_regs->phy_i2cm_operation_addr,
 345                 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
 346
 347         hdmi_phy_wait_i2c_done(1000);
 348 }
 349
 350 static void hdmi_phy_enable_power(u8 enable)
 351 {
 352         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
 353                      enable << HDMI_PHY_CONF0_PDZ_OFFSET);
 354 }
 355
 356 static void hdmi_phy_enable_tmds(u8 enable)
 357 {
 358         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
 359                      enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
 360 }
 361
 362 static void hdmi_phy_enable_spare(u8 enable)
 363 {
 364         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
 365                      enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
 366 }
 367
 368 static void hdmi_phy_gen2_pddq(u8 enable)
 369 {
 370         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
 371                      enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
 372 }
 373
 374 static void hdmi_phy_gen2_txpwron(u8 enable)
 375 {
 376         clrsetbits32(&hdmi_regs->phy_conf0,
 377                      HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
 378                      enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
 379 }
 380
 381 static void hdmi_phy_sel_data_en_pol(u8 enable)
 382 {
 383         clrsetbits32(&hdmi_regs->phy_conf0,
 384                      HDMI_PHY_CONF0_SELDATAENPOL_MASK,
 385                      enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
 386 }
 387
 388 static void hdmi_phy_sel_interface_control(u8 enable)
 389 {
 390         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
 391                      enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
 392 }
 393
 394 static int hdmi_phy_configure(u32 mpixelclock)
 395 {
 396         struct stopwatch pll_ready;
 397         u8 i, val;
 398
 399         write32(&hdmi_regs->mc_flowctrl,
 400                 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);
 401
 402         /* gen2 tx power off */
 403         hdmi_phy_gen2_txpwron(0);
 404
 405         /* gen2 pddq */
 406         hdmi_phy_gen2_pddq(1);
 407
 408         /* phy reset */
 409         write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_DEASSERT);
 410         write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_ASSERT);
 411         write32(&hdmi_regs->mc_heacphy_rst, HDMI_MC_HEACPHY_RST_ASSERT);
 412
 413         hdmi_phy_test_clear(1);
 414         write32(&hdmi_regs->phy_i2cm_slave_addr,
 415                 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
 416         hdmi_phy_test_clear(0);
 417
 418         /* pll/mpll cfg - always match on final entry */
 419         for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
 420                 if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
 421                         break;
 422
 423         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
 424         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
 425         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
 426
 427         hdmi_phy_i2c_write(0x0000, PHY_PLLPHBYCTRL);
 428         hdmi_phy_i2c_write(0x0006, PHY_PLLCLKBISTPHASE);
 429
 430         for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
 431                 if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
 432                         break;
 433
 434         /*
 435          * resistance term 133ohm cfg
 436          * preemp cgf 0.00
 437          * tx/ck lvl 10
 438          */
 439         hdmi_phy_i2c_write(rockchip_phy_config[i].term, PHY_TXTERM);
 440         hdmi_phy_i2c_write(rockchip_phy_config[i].sym_ctr, PHY_CKSYMTXCTRL);
 441         hdmi_phy_i2c_write(rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
 442
 443         /* remove clk term */
 444         hdmi_phy_i2c_write(0x8000, PHY_CKCALCTRL);
 445
 446         hdmi_phy_enable_power(1);
 447
 448         /* toggle tmds enable */
 449         hdmi_phy_enable_tmds(0);
 450         hdmi_phy_enable_tmds(1);
 451
 452         /* gen2 tx power on */
 453         hdmi_phy_gen2_txpwron(1);
 454         hdmi_phy_gen2_pddq(0);
 455
 456         hdmi_phy_enable_spare(1);
 457
 458         /* wait for phy pll lock */
 459         stopwatch_init_msecs_expire(&pll_ready, 5);
 460         do {
 461                 val = read32(&hdmi_regs->phy_stat0);
 462                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
 463                         return 0;
 464
 465                 udelay(100);
 466         } while (!stopwatch_expired(&pll_ready));
 467
 468         return -1;
 469 }
 470
 471 static int hdmi_phy_init(u32 mpixelclock)
 472 {
 473         int i, ret;
 474
 475         /* hdmi phy spec says to do the phy initialization sequence twice */
 476         for (i = 0; i < 2; i++) {
 477                 hdmi_phy_sel_data_en_pol(1);
 478                 hdmi_phy_sel_interface_control(0);
 479                 hdmi_phy_enable_tmds(0);
 480                 hdmi_phy_enable_power(0);
 481
 482                 /* enable csc */
 483                 ret = hdmi_phy_configure(mpixelclock);
 484                 if (ret) {
 485                         hdmi_debug("hdmi phy config failure %d\n", ret);
 486                         return ret;
 487                 }
 488         }
 489
 490         return 0;
 491 }
 492
 493 static void hdmi_av_composer(const struct edid *edid)
 494 {
 495         u8 mdataenablepolarity = 1;
 496         u8 inv_val;
 497
 498         /* set up hdmi_fc_invidconf */
 499         inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
 500
 501         inv_val |= ((edid->mode.pvsync == '+') ?
 502                    HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
 503                    HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
 504
 505         inv_val |= ((edid->mode.phsync == '+') ?
 506                    HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
 507                    HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
 508
 509         inv_val |= (mdataenablepolarity ?
 510                    HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
 511                    HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
 512
 513         inv_val |= (edid->hdmi_monitor_detected ?
 514                    HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
 515                    HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
 516
 517         inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
 518
 519         inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
 520
 521         write32(&hdmi_regs->fc_invidconf, inv_val);
 522
 523         /* set up horizontal active pixel width */
 524         write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
 525         write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
 526
 527         /* set up vertical active lines */
 528         write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
 529         write32(&hdmi_regs->fc_invactv0, edid->mode.va);
 530
 531         /* set up horizontal blanking pixel region width */
 532         write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
 533         write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
 534
 535         /* set up vertical blanking pixel region width */
 536         write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
 537
 538         /* set up hsync active edge delay width (in pixel clks) */
 539         write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
 540         write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
 541
 542         /* set up vsync active edge delay (in lines) */
 543         write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
 544
 545         /* set up hsync active pulse width (in pixel clks) */
 546         write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
 547         write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
 548
 549         /* set up vsync active edge delay (in lines) */
 550         write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
 551 }
 552
 553 /* hdmi initialization step b.4 */
 554 static void hdmi_enable_video_path(void)
 555 {
 556         u8 clkdis;
 557
 558         /* control period minimum duration */
 559         write32(&hdmi_regs->fc_ctrldur, 12);
 560         write32(&hdmi_regs->fc_exctrldur, 32);
 561         write32(&hdmi_regs->fc_exctrlspac, 1);
 562
 563         /* set to fill tmds data channels */
 564         write32(&hdmi_regs->fc_ch0pream, 0x0b);
 565         write32(&hdmi_regs->fc_ch1pream, 0x16);
 566         write32(&hdmi_regs->fc_ch2pream, 0x21);
 567
 568         /* enable pixel clock and tmds data path */
 569         clkdis = 0x7f;
 570         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
 571         write32(&hdmi_regs->mc_clkdis, clkdis);
 572
 573         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
 574         write32(&hdmi_regs->mc_clkdis, clkdis);
 575
 576         clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 577         write32(&hdmi_regs->mc_clkdis, clkdis);
 578 }
 579
 580 /* workaround to clear the overflow condition */
 581 static void hdmi_clear_overflow(void)
 582 {
 583         u8 val, count;
 584
 585         /* tmds software reset */
 586         write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);
 587
 588         val = read32(&hdmi_regs->fc_invidconf);
 589
 590         for (count = 0; count < 4; count++)
 591                 write32(&hdmi_regs->fc_invidconf, val);
 592 }
 593
 594 static void hdmi_audio_set_format(void)
 595 {
 596         write32(&hdmi_regs->aud_conf0,
 597                 HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0);
 598
 599         write32(&hdmi_regs->aud_conf1,
 600                 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
 601                 HDMI_AUD_CONF1_I2S_WIDTH_16BIT);
 602
 603         write32(&hdmi_regs->aud_conf2, 0x00);
 604 }
 605
 606 static void hdmi_audio_fifo_reset(void)
 607 {
 608         write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ);
 609         write32(&hdmi_regs->aud_conf0, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST);
 610
 611         write32(&hdmi_regs->aud_int, 0x00);
 612         write32(&hdmi_regs->aud_int1, 0x00);
 613 }
 614
 615 static int hdmi_setup(const struct edid *edid)
 616 {
 617         int ret;
 618
 619         hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
 620                    edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
 621
 622         hdmi_av_composer(edid);
 623
 624         ret = hdmi_phy_init(edid->mode.pixel_clock);
 625         if (ret)
 626                 return ret;
 627
 628         hdmi_enable_video_path();
 629
 630         hdmi_audio_fifo_reset();
 631         hdmi_audio_set_format();
 632         hdmi_audio_set_samplerate(edid->mode.pixel_clock);
 633
 634         hdmi_video_packetize();
 635         hdmi_video_csc();
 636         hdmi_video_sample();
 637
 638         hdmi_clear_overflow();
 639
 640         return 0;
 641 }
 642
 643 static void hdmi_init_interrupt(void)
 644 {
 645         u8 ih_mute;
 646
 647         /*
 648          * boot up defaults are:
 649          * hdmi_ih_mute   = 0x03 (disabled)
 650          * hdmi_ih_mute_* = 0x00 (enabled)
 651          *
 652          * disable top level interrupt bits in hdmi block
 653          */
 654         ih_mute = read32(&hdmi_regs->ih_mute) |
 655                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
 656                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
 657
 658         write32(&hdmi_regs->ih_mute, ih_mute);
 659
 660         /* enable i2c master done irq */
 661         write32(&hdmi_regs->i2cm_int, ~0x04);
 662
 663         /* enable i2c client nack % arbitration error irq */
 664         write32(&hdmi_regs->i2cm_ctlint, ~0x44);
 665
 666         /* enable phy i2cm done irq */
 667         write32(&hdmi_regs->phy_i2cm_int_addr, HDMI_PHY_I2CM_INT_ADDR_DONE_POL);
 668
 669         /* enable phy i2cm nack & arbitration error irq */
 670         write32(&hdmi_regs->phy_i2cm_ctlint_addr,
 671                 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
 672                 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL);
 673
 674         /* enable cable hot plug irq */
 675         write32(&hdmi_regs->phy_mask0, (u8)~HDMI_PHY_HPD);
 676
 677         /* clear hotplug interrupts */
 678         write32(&hdmi_regs->ih_phy_stat0, HDMI_IH_PHY_STAT0_HPD);
 679 }
 680
 681 static u8 hdmi_get_plug_in_status(void)
 682 {
 683         u8 val = read32(&hdmi_regs->phy_stat0) & HDMI_PHY_HPD;
 684
 685         return !!(val);
 686 }
 687
 688 static int hdmi_wait_for_hpd(void)
 689 {
 690         struct stopwatch hpd;
 691
 692         stopwatch_init_msecs_expire(&hpd, 30000);
 693         do {
 694                 if (hdmi_get_plug_in_status())
 695                         return 0;
 696                 udelay(100);
 697         } while (!stopwatch_expired(&hpd));
 698
 699         return -1;
 700 }
 701
 702 static int hdmi_ddc_wait_i2c_done(int msec)
 703 {
 704         struct stopwatch ddci2c_done;
 705         u32 val;
 706
 707         stopwatch_init_msecs_expire(&ddci2c_done, msec);
 708         do {
 709                 val = read32(&hdmi_regs->ih_i2cm_stat0);
 710                 if (val & 0x2) {
 711                         write32(&hdmi_regs->ih_i2cm_stat0, val);
 712                         return 0;
 713                 }
 714
 715                 udelay(100);
 716         } while (!stopwatch_expired(&ddci2c_done));
 717
 718         return 1;
 719 }
 720
 721 static void hdmi_ddc_reset(void)
 722 {
 723         clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ,
 724                      HDMI_I2CM_SOFTRSTZ);
 725 }
 726
 727 static int hdmi_read_edid(int block, u8 *buff)
 728 {
 729         int shift = (block % 2) * 0x80;
 730         int edid_read_err = 0;
 731         u32 trytime = 5;
 732         u32 n, j, val;
 733
 734         /* set ddc i2c clk which derived from ddc_clk to 100kHz */
 735         write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a);
 736         write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d);
 737         clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
 738                         HDMI_I2CM_DIV_STD_MODE);
 739
 740         write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR);
 741         write32(&hdmi_regs->i2cm_segaddr, HDMI_I2CM_SEGADDR_DDC);
 742         write32(&hdmi_regs->i2cm_segptr, block >> 1);
 743
 744         while (trytime--) {
 745                 edid_read_err = 0;
 746
 747                 for (n = 0; n < HDMI_EDID_BLOCK_SIZE/8; n++) {
 748                         write32(&hdmi_regs->i2cmess, shift + 8 * n);
 749
 750                         if (block == 0)
 751                                 clrsetbits32(&hdmi_regs->i2cm_operation,
 752                                              HDMI_I2CM_OPT_RD8,
 753                                              HDMI_I2CM_OPT_RD8);
 754                         else
 755                                 clrsetbits32(&hdmi_regs->i2cm_operation,
 756                                              HDMI_I2CM_OPT_RD8_EXT,
 757                                              HDMI_I2CM_OPT_RD8_EXT);
 758
 759                         if (hdmi_ddc_wait_i2c_done(10)) {
 760                                 hdmi_ddc_reset();
 761                                 edid_read_err = 1;
 762                                 break;
 763                         }
 764
 765                         for (j = 0; j < 8; j++) {
 766                                 val = read32(&hdmi_regs->i2cm_buf0 + j);
 767                                 buff[8 * n + j] = val;
 768                         }
 769                 }
 770
 771                 if (!edid_read_err)
 772                         break;
 773         }
 774
 775         return edid_read_err;
 776 }
 777
 778 int rk_hdmi_get_edid(struct edid *edid)
 779 {
 780         u8 edid_buf[HDMI_EDID_BLOCK_SIZE * 2];
 781         u32 edid_size = HDMI_EDID_BLOCK_SIZE;
 782         gpio_t hdmi_i2c_sda = GPIO(7, C, 3);
 783         gpio_t hdmi_i2c_scl = GPIO(7, C, 4);
 784         int ret;
 785
 786         /* If SDA is low, try to clock once to fix it */
 787         gpio_input_pullup(hdmi_i2c_sda);
 788         if (gpio_get(hdmi_i2c_sda) == 0) {
 789                 gpio_output(hdmi_i2c_scl, 0);
 790                 udelay(1000);
 791                 gpio_input_pullup(hdmi_i2c_scl);
 792                 udelay(1000);
 793         }
 794
 795         /* HDMI I2C */
 796         write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA);
 797         write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL);
 798
 799         ret = hdmi_read_edid(0, edid_buf);
 800         if (ret) {
 801                 hdmi_debug("failed to read edid.\n");
 802                 return -1;
 803         }
 804
 805         if (edid_buf[0x7e] != 0) {
 806                 hdmi_read_edid(1, edid_buf + HDMI_EDID_BLOCK_SIZE);
 807                 edid_size += HDMI_EDID_BLOCK_SIZE;
 808         }
 809
 810         /* Assume usage of HDMI implies an external display in which case
 811          * we should be lenient about errors that the EDID decoder finds. */
 812         if (decode_edid(edid_buf, edid_size, edid) != EDID_CONFORMANT)
 813                 hdmi_debug("failed to decode edid.\n");
 814
 815         /* Try 480p for best compatibility. */
 816         if (set_display_mode(edid, EDID_MODE_640x480_60Hz))
 817                 hdmi_debug("failed to set mode to 640x480@60Hz\n");
 818
 819         return 0;
 820 }
 821
 822 int rk_hdmi_enable(const struct edid *edid)
 823 {
 824         hdmi_setup(edid);
 825
 826         return 0;
 827 }
 828
 829 int rk_hdmi_init(u32 vop_id)
 830 {
 831         int ret;
 832         u32 val;
 833
 834         /* hdmi source select hdmi controller */
 835         write32(&rk3288_grf->soc_con6, RK_SETBITS(1 << 15));
 836
 837         /* hdmi data from vop id */
 838         val = (vop_id == 1) ? RK_SETBITS(1 << 4) : RK_CLRBITS(1 << 4);
 839         write32(&rk3288_grf->soc_con6, val);
 840
 841         ret = hdmi_wait_for_hpd();
 842         if (ret < 0) {
 843                 hdmi_debug("hdmi can not get hpd signal\n");
 844                 return -1;
 845         }
 846
 847         hdmi_init_interrupt();
 848
 849         hdmi_debug("hdmi init success\n");
 850
 851         return 0;
 852 }