src/soc/rockchip/rk3288/clock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <device/mmio.h>
  16 #include <assert.h>
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <lib.h>
  20 #include <soc/addressmap.h>
  21 #include <soc/clock.h>
  22 #include <soc/grf.h>
  23 #include <soc/i2c.h>
  24 #include <soc/soc.h>
  25 #include <stdint.h>
  26 #include <string.h>
  27
  28 struct pll_div {
  29         u32     nr;
  30         u32     nf;
  31         u32     no;
  32 };
  33
  34 struct rk3288_cru_reg {
  35         u32 cru_apll_con[4];
  36         u32 cru_dpll_con[4];
  37         u32 cru_cpll_con[4];
  38         u32 cru_gpll_con[4];
  39         u32 cru_npll_con[4];
  40         u32 cru_mode_con;
  41         u32 reserved0[3];
  42         u32 cru_clksel_con[43];
  43         u32 reserved1[21];
  44         u32 cru_clkgate_con[19];
  45         u32 reserved2;
  46         u32 cru_glb_srst_fst_value;
  47         u32 cru_glb_srst_snd_value;
  48         u32 cru_softrst_con[12];
  49         u32 cru_misc_con;
  50         u32 cru_glb_cnt_th;
  51         u32 cru_glb_rst_con;
  52         u32 reserved3;
  53         u32 cru_glb_rst_st;
  54         u32 reserved4;
  55         u32 cru_sdmmc_con[2];
  56         u32 cru_sdio0_con[2];
  57         u32 cru_sdio1_con[2];
  58         u32 cru_emmc_con[2];
  59 };
  60 check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c);
  61
  62 static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
  63
  64 #define PLL_DIVISORS(hz, _nr, _no) {\
  65         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  66         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  67                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  68                        "divisors on line " STRINGIFY(__LINE__));
  69
  70 /* Keep divisors as low as possible to reduce jitter and power usage. */
  71 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  72 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  73
  74 /* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
  75 static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
  76 static const struct pll_div apll_1416_cfg = PLL_DIVISORS(1416*MHz, 1, 1);
  77 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
  78 static const struct pll_div *apll_cfgs[] = {
  79         [APLL_1800_MHZ] = &apll_1800_cfg,
  80         [APLL_1416_MHZ] = &apll_1416_cfg,
  81         [APLL_600_MHZ] = &apll_600_cfg,
  82 };
  83
  84 /*******************PLL CON0 BITS***************************/
  85 #define PLL_OD_MSK      (0x0F)
  86
  87 #define PLL_NR_MSK      (0x3F << 8)
  88 #define PLL_NR_SHIFT    (8)
  89
  90 /*******************PLL CON1 BITS***************************/
  91 #define PLL_NF_MSK      (0x1FFF)
  92
  93 /*******************PLL CON2 BITS***************************/
  94 #define PLL_BWADJ_MSK   (0x0FFF)
  95
  96 /*******************PLL CON3 BITS***************************/
  97 #define PLL_RESET_MSK   (1 << 5)
  98 #define PLL_RESET       (1 << 5)
  99 #define PLL_RESET_RESUME        (0 << 5)
 100
 101 /*******************CLKSEL0 BITS***************************/
 102 /* core clk pll sel: amr or general */
 103 #define CORE_SEL_PLL_MSK        (1 << 15)
 104 #define CORE_SEL_APLL   (0 << 15)
 105 #define CORE_SEL_GPLL   (1 << 15)
 106
 107 /* a12 core clock div: clk_core = clk_src / (div_con + 1) */
 108 #define A12_DIV_SHIFT   (8)
 109 #define A12_DIV_MSK     (0x1F << 8)
 110
 111 /* mp core axi clock div: clk = clk_src / (div_con + 1) */
 112 #define MP_DIV_SHIFT    (4)
 113 #define MP_DIV_MSK      (0xF << 4)
 114
 115 /* m0 core axi clock div: clk = clk_src / (div_con + 1) */
 116 #define M0_DIV_MSK      (0xF)
 117
 118 /*******************CLKSEL1 BITS***************************/
 119 /* pd bus clk pll sel: codec or general */
 120 #define PD_BUS_SEL_PLL_MSK      (1 << 15)
 121 #define PD_BUS_SEL_CPLL (0 << 15)
 122 #define PD_BUS_SEL_GPLL (1 << 15)
 123
 124 /* pd bus pclk div:
 125  * pclk = pd_bus_aclk /(div + 1)
 126  */
 127 #define PD_BUS_PCLK_DIV_SHIFT   (12)
 128 #define PD_BUS_PCLK_DIV_MSK     (0x7 << 12)
 129
 130 /* pd bus hclk div:
 131  * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1
 132  */
 133 #define PD_BUS_HCLK_DIV_SHIFT   (8)
 134 #define PD_BUS_HCLK_DIV_MSK     (0x3 << 8)
 135
 136 /* pd bus aclk div:
 137  * pd_bus_aclk = pd_bus_src_clk /(div0 * div1)
 138  */
 139 #define PD_BUS_ACLK_DIV0_SHIFT  (3)
 140 #define PD_BUS_ACLK_DIV0_MASK   (0x1f << 3)
 141 #define PD_BUS_ACLK_DIV1_SHIFT  (0)
 142 #define PD_BUS_ACLK_DIV1_MASK   (0x7 << 0)
 143
 144 /*******************CLKSEL10 BITS***************************/
 145 /* peripheral bus clk pll sel: codec or general */
 146 #define PERI_SEL_PLL_MSK        (1 << 15)
 147 #define PERI_SEL_CPLL   (0 << 15)
 148 #define PERI_SEL_GPLL   (1 << 15)
 149
 150 /* peripheral bus pclk div:
 151  * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 152  */
 153 #define PERI_PCLK_DIV_SHIFT     (12)
 154 #define PERI_PCLK_DIV_MSK       (0x7 << 12)
 155
 156 /* peripheral bus hclk div:
 157  * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1
 158  */
 159 #define PERI_HCLK_DIV_SHIFT     (8)
 160 #define PERI_HCLK_DIV_MSK       (0x3 << 8)
 161
 162 /* peripheral bus aclk div:
 163  * aclk_periph =
 164  * periph_clk_src / (peri_aclk_div_con + 1)
 165  */
 166 #define PERI_ACLK_DIV_SHIFT     (0x0)
 167 #define PERI_ACLK_DIV_MSK       (0x1F)
 168
 169 /*******************CLKSEL37 BITS***************************/
 170 #define L2_DIV_MSK      (0x7)
 171
 172 #define ATCLK_DIV_MSK   (0x1F << 4)
 173 #define ATCLK_DIV_SHIFT (4)
 174
 175 #define PCLK_DBG_DIV_MSK        (0x1F << 9)
 176 #define PCLK_DBG_DIV_SHIFT      (9)
 177
 178 #define APLL_MODE_MSK   (0x3)
 179 #define APLL_MODE_SLOW  (0)
 180 #define APLL_MODE_NORM  (1)
 181
 182 #define DPLL_MODE_MSK   (0x3 << 4)
 183 #define DPLL_MODE_SLOW  (0 << 4)
 184 #define DPLL_MODE_NORM  (1 << 4)
 185
 186 #define CPLL_MODE_MSK   (0x3 << 8)
 187 #define CPLL_MODE_SLOW  (0 << 8)
 188 #define CPLL_MODE_NORM  (1 << 8)
 189
 190 #define GPLL_MODE_MSK   (0x3 << 12)
 191 #define GPLL_MODE_SLOW  (0 << 12)
 192 #define GPLL_MODE_NORM  (1 << 12)
 193
 194 #define NPLL_MODE_MSK   (0x3 << 14)
 195 #define NPLL_MODE_SLOW  (0 << 14)
 196 #define NPLL_MODE_NORM  (1 << 14)
 197
 198 #define SOCSTS_DPLL_LOCK        (1 << 5)
 199 #define SOCSTS_APLL_LOCK        (1 << 6)
 200 #define SOCSTS_CPLL_LOCK        (1 << 7)
 201 #define SOCSTS_GPLL_LOCK        (1 << 8)
 202 #define SOCSTS_NPLL_LOCK        (1 << 9)
 203
 204 #define VCO_MAX_KHZ     (2200 * (MHz/KHz))
 205 #define VCO_MIN_KHZ     (440 * (MHz/KHz))
 206 #define OUTPUT_MAX_KHZ  (2200 * (MHz/KHz))
 207 #define OUTPUT_MIN_KHZ  27500
 208 #define FREF_MAX_KHZ    (2200 * (MHz/KHz))
 209 #define FREF_MIN_KHZ    269
 210
 211 static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 212 {
 213         /* All PLLs have same VCO and output frequency range restrictions. */
 214         u32 vco_khz = OSC_HZ/KHz * div->nf / div->nr;
 215         u32 output_khz = vco_khz / div->no;
 216
 217         printk(BIOS_DEBUG, "Configuring PLL at %p with NF = %d, NR = %d and "
 218                "NO = %d (VCO = %uKHz, output = %uKHz)\n",
 219                pll_con, div->nf, div->nr, div->no, vco_khz, output_khz);
 220         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 221                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 222                (div->no == 1 || !(div->no % 2)));
 223
 224         /* enter rest */
 225         write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK));
 226
 227         write32(&pll_con[0],
 228                 RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) |
 229                 RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)));
 230
 231         write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)));
 232
 233         write32(&pll_con[2],
 234                 RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)));
 235
 236         udelay(10);
 237
 238         /* return form rest */
 239         write32(&pll_con[3], RK_CLRBITS(PLL_RESET_MSK));
 240
 241         return 0;
 242 }
 243
 244 void rkclk_init(void)
 245 {
 246         u32 aclk_div;
 247         u32 hclk_div;
 248         u32 pclk_div;
 249
 250         /* pll enter slow-mode */
 251         write32(&cru_ptr->cru_mode_con,
 252                 RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) |
 253                 RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW));
 254
 255         /* init pll */
 256         rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg);
 257         rkclk_set_pll(&cru_ptr->cru_cpll_con[0], &cpll_init_cfg);
 258
 259         /* waiting for pll lock */
 260         while (1) {
 261                 if ((read32(&rk3288_grf->soc_status[1])
 262                         & (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 263                         == (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 264                         break;
 265                 udelay(1);
 266         }
 267
 268         /*
 269          * pd_bus clock pll source selection and
 270          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 271          */
 272         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 273         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 274         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 275         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 276                 PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2));
 277
 278         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 279         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 280                 PD_BUS_ACLK_HZ && pclk_div <= 0x7);
 281
 282         write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) |
 283                 RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK,
 284                               pclk_div << PD_BUS_PCLK_DIV_SHIFT) |
 285                 RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK,
 286                               hclk_div << PD_BUS_HCLK_DIV_SHIFT) |
 287                 RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK,
 288                               aclk_div << PD_BUS_ACLK_DIV0_SHIFT) |
 289                 RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0));
 290
 291         /*
 292          * peri clock pll source selection and
 293          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 294          */
 295         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 296         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 297
 298         hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 299         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 300                 PERI_ACLK_HZ && (hclk_div <= 0x2));
 301
 302         pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 303         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 304                 PERI_ACLK_HZ && (pclk_div <= 0x3));
 305
 306         write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) |
 307                 RK_CLRSETBITS(PERI_PCLK_DIV_MSK,
 308                               pclk_div << PERI_PCLK_DIV_SHIFT) |
 309                 RK_CLRSETBITS(PERI_HCLK_DIV_MSK,
 310                               hclk_div << PERI_HCLK_DIV_SHIFT) |
 311                 RK_CLRSETBITS(PERI_ACLK_DIV_MSK,
 312                               aclk_div << PERI_ACLK_DIV_SHIFT));
 313
 314         /* PLL enter normal-mode */
 315         write32(&cru_ptr->cru_mode_con,
 316                 RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
 317                 RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM));
 318
 319 }
 320
 321 void rkclk_configure_cpu(enum apll_frequencies apll_freq)
 322 {
 323         /* pll enter slow-mode */
 324         write32(&cru_ptr->cru_mode_con,
 325                 RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
 326
 327         rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]);
 328
 329         /* waiting for pll lock */
 330         while (1) {
 331                 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK)
 332                         break;
 333                 udelay(1);
 334         }
 335
 336         /*
 337          * core clock pll source selection and
 338          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 339          * core clock select apll, apll clk = 1800MHz
 340          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 341          */
 342         write32(&cru_ptr->cru_clksel_con[0], RK_CLRBITS(CORE_SEL_PLL_MSK) |
 343                 RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) |
 344                 RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) |
 345                 RK_CLRSETBITS(M0_DIV_MSK, 1 << 0));
 346
 347         /*
 348          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 349          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 350          */
 351         write32(&cru_ptr->cru_clksel_con[37],
 352                 RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) |
 353                 RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) |
 354                 RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)));
 355
 356         /* PLL enter normal-mode */
 357         write32(&cru_ptr->cru_mode_con,
 358                 RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM));
 359 }
 360
 361 void rkclk_configure_ddr(unsigned int hz)
 362 {
 363         struct pll_div dpll_cfg;
 364
 365         switch (hz) {
 366         case 300*MHz:
 367                 dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2};
 368                 break;
 369         case 533*MHz:   /* actually 533.3P MHz */
 370                 dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};
 371                 break;
 372         case 666*MHz:   /* actually 666.6P MHz */
 373                 dpll_cfg = (struct pll_div){.nf = 500, .nr = 9, .no = 2};
 374                 break;
 375         case 800*MHz:
 376                 dpll_cfg = (struct pll_div){.nf = 100, .nr = 3, .no = 1};
 377                 break;
 378         default:
 379                 die("Unsupported SDRAM frequency, add to clock.c!");
 380         }
 381
 382         /* pll enter slow-mode */
 383         write32(&cru_ptr->cru_mode_con,
 384                 RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW));
 385
 386         rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg);
 387
 388         /* waiting for pll lock */
 389         while (1) {
 390                 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK)
 391                         break;
 392                 udelay(1);
 393         }
 394
 395         /* PLL enter normal-mode */
 396         write32(&cru_ptr->cru_mode_con,
 397                 RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM));
 398 }
 399
 400 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
 401 {
 402         u32 phy_ctl_srstn_shift = 4 + 5 * ch;
 403         u32 ctl_psrstn_shift = 3 + 5 * ch;
 404         u32 ctl_srstn_shift = 2 + 5 * ch;
 405         u32 phy_psrstn_shift = 1 + 5 * ch;
 406         u32 phy_srstn_shift = 5 * ch;
 407
 408         write32(&cru_ptr->cru_softrst_con[10],
 409                 RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
 410                               phy << phy_ctl_srstn_shift) |
 411                 RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) |
 412                 RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) |
 413                 RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) |
 414                 RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift));
 415 }
 416
 417 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n)
 418 {
 419         u32 phy_ctl_srstn_shift = 4 + 5 * ch;
 420
 421         write32(&cru_ptr->cru_softrst_con[10],
 422                 RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
 423                 n << phy_ctl_srstn_shift));
 424 }
 425
 426 void rkclk_configure_spi(unsigned int bus, unsigned int hz)
 427 {
 428         int src_clk_div = GPLL_HZ / hz;
 429
 430         assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ));
 431
 432         switch (bus) {  /*select gpll as spi src clk, and set div*/
 433         case 0:
 434                 write32(&cru_ptr->cru_clksel_con[25],
 435                         RK_CLRSETBITS(1 << 7 | 0x1f << 0,
 436                                       1 << 7 | (src_clk_div - 1) << 0));
 437                 break;
 438         case 1:
 439                 write32(&cru_ptr->cru_clksel_con[25],
 440                         RK_CLRSETBITS(1 << 15 | 0x1f << 8,
 441                                       1 << 15 | (src_clk_div - 1) << 8));
 442                 break;
 443         case 2:
 444                 write32(&cru_ptr->cru_clksel_con[39],
 445                         RK_CLRSETBITS(1 << 7 | 0x1f << 0,
 446                                       1 << 7 | (src_clk_div - 1) << 0));
 447                 break;
 448         default:
 449                 printk(BIOS_ERR, "do not support this spi bus\n");
 450         }
 451 }
 452
 453 static u32 clk_gcd(u32 a, u32 b)
 454 {
 455         while (b != 0) {
 456                 int r = b;
 457                 b = a % b;
 458                 a = r;
 459         }
 460         return a;
 461 }
 462
 463 void rkclk_configure_i2s(unsigned int hz)
 464 {
 465         int n, d;
 466         int v;
 467
 468         /* i2s source clock: gpll
 469            i2s0_outclk_sel: clk_i2s
 470            i2s0_clk_sel: divider output from fraction
 471            i2s0_pll_div_con: 0*/
 472         write32(&cru_ptr->cru_clksel_con[4],
 473                 RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
 474                               1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
 475
 476         /* set frac divider */
 477         v = clk_gcd(GPLL_HZ, hz);
 478         n = (GPLL_HZ / v) & (0xffff);
 479         d = (hz / v) & (0xffff);
 480         assert(hz == GPLL_HZ / n * d);
 481         write32(&cru_ptr->cru_clksel_con[8], d << 16 | n);
 482 }
 483
 484 void rkclk_configure_crypto(unsigned int hz)
 485 {
 486         u32 div = PD_BUS_ACLK_HZ / hz;
 487
 488         assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ));
 489         assert(hz <= 150*MHz);  /* Suggested max in TRM. */
 490         write32(&cru_ptr->cru_clksel_con[26],
 491                 RK_CLRSETBITS(0x3 << 6, (div - 1) << 6));
 492 }
 493
 494 void rkclk_configure_tsadc(unsigned int hz)
 495 {
 496         u32 div;
 497         u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/
 498
 499         div = src_clk / hz;
 500         assert((div - 1 <= 63) && (div * hz == 32 * KHz));
 501         write32(&cru_ptr->cru_clksel_con[2],
 502                 RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
 503 }
 504
 505 static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
 506 {
 507         u32 ref_khz = OSC_HZ / KHz, nr, nf = 0;
 508         u32 fref_khz;
 509         u32 diff_khz, best_diff_khz;
 510         const u32 max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 511         u32 vco_khz;
 512         u32 no = 1;
 513         u32 freq_khz = freq_hz / KHz;
 514
 515         if (!freq_hz) {
 516                 printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__);
 517                 return -1;
 518         }
 519
 520         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 521         if (ext_div) {
 522                 *ext_div = DIV_ROUND_UP(no, max_no);
 523                 no = DIV_ROUND_UP(no, *ext_div);
 524         }
 525
 526         /* only even divisors (and 1) are supported */
 527         if (no > 1)
 528                 no = DIV_ROUND_UP(no, 2) * 2;
 529
 530         vco_khz = freq_khz * no;
 531         if (ext_div)
 532                 vco_khz *= *ext_div;
 533
 534         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 535                 printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
 536                 " for Frequency (%uHz).\n", __func__, freq_hz);
 537                 return -1;
 538         }
 539
 540         div->no = no;
 541
 542         best_diff_khz = vco_khz;
 543         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 544                 fref_khz = ref_khz / nr;
 545                 if (fref_khz < FREF_MIN_KHZ)
 546                         break;
 547                 if (fref_khz > FREF_MAX_KHZ)
 548                         continue;
 549
 550                 nf = vco_khz / fref_khz;
 551                 if (nf >= max_nf)
 552                         continue;
 553                 diff_khz = vco_khz - nf * fref_khz;
 554                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 555                         nf++;
 556                         diff_khz = fref_khz - diff_khz;
 557                 }
 558
 559                 if (diff_khz >= best_diff_khz)
 560                         continue;
 561
 562                 best_diff_khz = diff_khz;
 563                 div->nr = nr;
 564                 div->nf = nf;
 565         }
 566
 567         if (best_diff_khz > 4 * (MHz/KHz)) {
 568                 printk(BIOS_ERR, "%s: Failed to match output frequency %u, "
 569                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 570                        best_diff_khz * KHz);
 571                 return -1;
 572         }
 573
 574         return 0;
 575 }
 576
 577 void rkclk_configure_edp(void)
 578 {
 579         /* clk_edp_24M source: 24M */
 580         write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15));
 581
 582         /* rst edp */
 583         write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15));
 584         udelay(1);
 585         write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15));
 586 }
 587
 588 void rkclk_configure_hdmi(void)
 589 {
 590         /* enable pclk hdmi ctrl */
 591         write32(&cru_ptr->cru_clkgate_con[16], RK_CLRBITS(1 << 9));
 592
 593         /* software reset hdmi */
 594         write32(&cru_ptr->cru_softrst_con[7], RK_SETBITS(1 << 9));
 595         udelay(1);
 596         write32(&cru_ptr->cru_softrst_con[7], RK_CLRBITS(1 << 9));
 597 }
 598
 599 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
 600 {
 601         u32 div;
 602
 603         /* vop aclk source clk: cpll */
 604         div = CPLL_HZ / aclk_hz;
 605         assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ));
 606
 607         switch (vop_id) {
 608         case 0:
 609                 write32(&cru_ptr->cru_clksel_con[31],
 610                         RK_CLRSETBITS(3 << 6 | 0x1f << 0,
 611                                       0 << 6 | (div - 1) << 0));
 612                 break;
 613
 614         case 1:
 615                 write32(&cru_ptr->cru_clksel_con[31],
 616                         RK_CLRSETBITS(3 << 14 | 0x1f << 8,
 617                                       0 << 14 | (div - 1) << 8));
 618                 break;
 619         }
 620 }
 621
 622 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
 623 {
 624         struct pll_div npll_config = {0};
 625         u32 lcdc_div;
 626
 627         if (pll_para_config(dclk_hz, &npll_config, &lcdc_div))
 628                 return -1;
 629
 630         /* npll enter slow-mode */
 631         write32(&cru_ptr->cru_mode_con,
 632                 RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW));
 633
 634         rkclk_set_pll(&cru_ptr->cru_npll_con[0], &npll_config);
 635
 636         /* waiting for pll lock */
 637         while (1) {
 638                 if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 639                         break;
 640                 udelay(1);
 641         }
 642
 643         /* npll enter normal-mode */
 644         write32(&cru_ptr->cru_mode_con,
 645                 RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM));
 646
 647         /* vop dclk source clk: npll,dclk_div: 1 */
 648         switch (vop_id) {
 649         case 0:
 650                 write32(&cru_ptr->cru_clksel_con[27],
 651                         RK_CLRSETBITS(0xff << 8 | 3 << 0,
 652                                       (lcdc_div - 1) << 8 | 2 << 0));
 653                 break;
 654
 655         case 1:
 656                 write32(&cru_ptr->cru_clksel_con[29],
 657                         RK_CLRSETBITS(0xff << 8 | 3 << 6,
 658                                       (lcdc_div - 1) << 8 | 2 << 6));
 659                 break;
 660         }
 661         return 0;
 662 }
 663
 664 int rkclk_was_watchdog_reset(void)
 665 {
 666         /* Bits 5 and 4 are "second" and "first" global watchdog reset. */
 667         return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
 668 }
 669
 670 unsigned int rkclk_i2c_clock_for_bus(unsigned int bus)
 671 {
 672         /*i2c0,i2c2 src clk from pd_bus_pclk
 673         other i2c src clk from peri_pclk
 674         */
 675         switch (bus) {
 676         case 0:
 677         case 2:
 678                 return PD_BUS_PCLK_HZ;
 679
 680         case 1:
 681         case 3:
 682         case 4:
 683         case 5:
 684                 return PERI_PCLK_HZ;
 685
 686         default:
 687                 return -1; /* Should never happen. */
 688         }
 689
 690 }