src/soc/qualcomm/ipq806x/clock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <device/mmio.h>
  16 #include <delay.h>
  17 #include <soc/clock.h>
  18 #include <types.h>
  19
  20 /**
  21  * uart_pll_vote_clk_enable - enables PLL8
  22  */
  23 void uart_pll_vote_clk_enable(unsigned int clk_dummy)
  24 {
  25         setbits32(BB_PLL_ENA_SC0_REG, BIT(8));
  26
  27         if (!clk_dummy)
  28                 while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
  29 }
  30
  31 /**
  32  * uart_set_rate_mnd - configures divider M and D values
  33  *
  34  * Sets the M, D parameters of the divider to generate the GSBI UART
  35  * apps clock.
  36  */
  37 static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
  38                 unsigned int n)
  39 {
  40         /* Assert MND reset. */
  41         setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
  42         /* Program M and D values. */
  43         write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
  44         /* Deassert MND reset. */
  45         clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
  46 }
  47
  48 /**
  49  * uart_branch_clk_enable_reg - enables branch clock
  50  *
  51  * Enables branch clock for GSBI UART port.
  52  */
  53 static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
  54 {
  55         setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
  56 }
  57
  58 /**
  59  * uart_local_clock_enable - configures N value and enables root clocks
  60  *
  61  * Sets the N parameter of the divider and enables root clock and
  62  * branch clocks for GSBI UART port.
  63  */
  64 static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
  65                                         unsigned int m)
  66 {
  67         unsigned int reg_val, uart_ns_val;
  68         void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port);
  69
  70         /*
  71         * Program the NS register, if applicable. NS registers are not
  72         * set in the set_rate path because power can be saved by deferring
  73         * the selection of a clocked source until the clock is enabled.
  74         */
  75         reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
  76         reg_val &= ~(Uart_clk_ns_mask);
  77         uart_ns_val =  NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3);
  78         reg_val |= (uart_ns_val & Uart_clk_ns_mask);
  79         write32(reg, reg_val);
  80
  81         /* enable MNCNTR_EN */
  82         reg_val = read32(reg);
  83         reg_val |= BIT(8);
  84         write32(reg, reg_val);
  85
  86         /* set source to PLL8 running @384MHz */
  87         reg_val = read32(reg);
  88         reg_val |= 0x3;
  89         write32(reg, reg_val);
  90
  91         /* Enable root. */
  92         reg_val |= Uart_en_mask;
  93         write32(reg, reg_val);
  94         uart_branch_clk_enable_reg(gsbi_port);
  95 }
  96
  97 /**
  98  * uart_set_gsbi_clk - enables HCLK for UART GSBI port
  99  */
 100 static void uart_set_gsbi_clk(unsigned int gsbi_port)
 101 {
 102         setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
 103 }
 104
 105 /**
 106  * uart_clock_config - configures UART clocks
 107  *
 108  * Configures GSBI UART dividers, enable root and branch clocks.
 109  */
 110 void uart_clock_config(unsigned int gsbi_port, unsigned int m,
 111                 unsigned int n, unsigned int d, unsigned int clk_dummy)
 112 {
 113         uart_set_rate_mnd(gsbi_port, m, d);
 114         uart_pll_vote_clk_enable(clk_dummy);
 115         uart_local_clock_enable(gsbi_port, n, m);
 116         uart_set_gsbi_clk(gsbi_port);
 117 }
 118
 119 /**
 120  * nand_clock_config - configure NAND controller clocks
 121  *
 122  * Enable clocks to EBI2. Must be invoked before touching EBI2
 123  * registers.
 124  */
 125 void nand_clock_config(void)
 126 {
 127         write32(EBI2_CLK_CTL_REG,
 128                 CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1));
 129
 130         /* Wait for clock to stabilize. */
 131         udelay(10);
 132 }
 133
 134 /**
 135  * usb_clock_config - configure USB controller clocks and reset the controller
 136  */
 137 void usb_clock_config(void)
 138 {
 139         /* Magic clock initialization numbers, nobody knows how they work... */
 140         write32(USB30_MASTER_CLK_CTL_REG, 0x10);
 141         write32(USB30_1_MASTER_CLK_CTL_REG, 0x10);
 142         write32(USB30_MASTER_CLK_MD, 0x500DF);
 143         write32(USB30_MASTER_CLK_NS, 0xE40942);
 144         write32(USB30_MOC_UTMI_CLK_MD, 0x100D7);
 145         write32(USB30_MOC_UTMI_CLK_NS, 0xD80942);
 146         write32(USB30_MOC_UTMI_CLK_CTL, 0x10);
 147         write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10);
 148
 149         write32(USB30_RESET,
 150                 1 << 5 |                /* assert port2 HS PHY async reset */
 151                 1 << 4 |                /* assert master async reset */
 152                 1 << 3 |                /* assert sleep async reset */
 153                 1 << 2 |                /* assert MOC UTMI async reset */
 154                 1 << 1 |                /* assert power-on async reset */
 155                 1 << 0);                /* assert PHY async reset */
 156         udelay(5);
 157         write32(USB30_RESET, 0);        /* deassert all USB resets again */
 158 }