src/soc/nvidia/tegra210/mipi-phy.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <soc/addressmap.h>
  16 #include <soc/clock.h>
  17 #include <device/device.h>
  18 #include <soc/nvidia/tegra/types.h>
  19 #include <soc/display.h>
  20 #include <soc/mipi_dsi.h>
  21 #include <soc/mipi_display.h>
  22 #include <soc/tegra_dsi.h>
  23 #include <soc/mipi-phy.h>
  24 #include <types.h>
  25
  26 int mipi_dphy_set_timing(struct tegra_dsi *dsi)
  27 {
  28
  29         u32 freq = (dsi->clk_rate * 2) / 1000000;
  30
  31         u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq)));
  32         u32 thstrial = (((3) + (DSI_PHY_TIMING_DIV((DSI_THSTRAIL_VAL(freq)),
  33                         freq))));
  34         u32 tdatzero = DSI_PHY_TIMING_DIV(((145) + (5 * (DSI_TBIT(freq)))),
  35                         (freq));
  36         u32 thsprepare = DSI_PHY_TIMING_DIV((65 + (5*(DSI_TBIT(freq)))), freq);
  37         u32 tclktrial = (DSI_PHY_TIMING_DIV(80, freq));
  38         u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))),
  39                         freq)));
  40         u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq));
  41         u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)) ;
  42         u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq));
  43         u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value
  44         u32 twakeup = 0x7F; //min = 1ms
  45
  46         u32 ttaget;
  47         u32 ttassure;
  48         u32 ttago;
  49         u32 value;
  50
  51         if (!ttlpx) {
  52                 ttaget = 5;
  53                 ttassure = 2;
  54                 ttago = 4;
  55         } else {
  56                 ttaget = 5 * ttlpx;
  57                 ttassure = 2 * ttlpx;
  58                 ttago = 4 * ttlpx;
  59         }
  60
  61         value = (thsdexit << 24) |
  62                 (thstrial << 16) |
  63                 (tdatzero << 8) |
  64                 (thsprepare << 0);
  65         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
  66
  67         value = (tclktrial << 24) |
  68                 (tclkpost << 16)  |
  69                 (tclkzero << 8) |
  70                 (ttlpx << 0);
  71         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
  72
  73         value = (tclkprepare << 16) |
  74                 (tclkpre << 8) |
  75                 (twakeup << 0);
  76         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
  77
  78         value = (ttaget << 16) |
  79                 (ttassure << 8) |
  80                 (ttago << 0),
  81         tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
  82         return 0;
  83 }