src/soc/mediatek/mt8183/spm.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <assert.h>
  16 #include <cbfs.h>
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <device/mmio.h>
  20 #include <endian.h>
  21 #include <soc/emi.h>
  22 #include <soc/spm.h>
  23 #include <timer.h>
  24
  25 #define BUF_SIZE (16 * KiB)
  26 static uint8_t spm_bin[BUF_SIZE] __aligned(8);
  27
  28 static int spm_register_init(void)
  29 {
  30         u32 pcm_fsm_sta;
  31
  32         write32(&mtk_spm->poweron_config_set,
  33                 SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB);
  34
  35         write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
  36         write32(&mtk_spm->pcm_pwr_io_en, 0);
  37
  38         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
  39                 PCM_SW_RESET_LSB);
  40         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
  41
  42         pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta);
  43
  44         if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) {
  45                 printk(BIOS_ERR, "PCM reset failed\n");
  46                 return -1;
  47         }
  48
  49         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
  50                 EN_IM_SLEEP_DVS_LSB);
  51         write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | EVENT_LOCK_EN_LSB |
  52                 SPM_SRAM_ISOINT_B_LSB | MIF_APBEN_LSB |
  53                 SCP_APB_INTERNAL_EN_LSB);
  54         write32(&mtk_spm->pcm_im_ptr, 0);
  55         write32(&mtk_spm->pcm_im_len, 0);
  56
  57         write32(&mtk_spm->spm_clk_con,
  58                 read32(&mtk_spm->spm_clk_con) | SYSCLK1_EN_CTRL |
  59                 SPM_LOCK_INFRA_DCM_LSB | EXT_SRCCLKEN_MASK |
  60                 CXO32K_REMOVE_EN_MD1_LSB |
  61                 CLKSQ1_SEL_CTRL_LSB | SRCLKEN0_EN_LSB | SYSCLK1_SRC_MASK_B);
  62
  63         write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
  64
  65         write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
  66         write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
  67         write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
  68
  69         write32(&mtk_spm->pcm_reg_data_ini,
  70                 read32(&mtk_spm->spm_power_on_val1));
  71         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
  72         write32(&mtk_spm->pcm_pwr_io_en, 0);
  73
  74         write32(&mtk_spm->ddr_en_dbc_len,
  75                 MD_DDR_EN_0_DBC_LEN |
  76                 MD_DDR_EN_1_DBC_LEN |
  77                 CONN_DDR_EN_DBC_LEN);
  78
  79         clrsetbits32(&mtk_spm->spare_ack_mask,
  80                      SPARE_ACK_MASK_B_BIT1,
  81                      SPARE_ACK_MASK_B_BIT0);
  82
  83         write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN);
  84         write32(&mtk_spm->spm_pc_trace_con,
  85                 SPM_PC_TRACE_OFFSET |
  86                 SPM_PC_TRACE_HW_EN_LSB);
  87
  88         setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB);
  89
  90         return 0;
  91 }
  92
  93 static int spm_code_swapping(void)
  94 {
  95         u32 con1;
  96
  97         con1 = read32(&mtk_spm->spm_wakeup_event_mask);
  98
  99         write32(&mtk_spm->spm_wakeup_event_mask,
 100                 con1 & ~WAKEUP_EVENT_MASK_B_BIT0);
 101         write32(&mtk_spm->spm_cpu_wakeup_event, 1);
 102
 103         if (!wait_us(SPM_CORE_TIMEOUT,
 104                      read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB)) {
 105                 printk(BIOS_ERR,
 106                        "timeout: r15=%#x, pcmsta=%#x, irqsta=%#x [%d]\n",
 107                        read32(&mtk_spm->pcm_reg15_data),
 108                        read32(&mtk_spm->pcm_fsm_sta),
 109                        read32(&mtk_spm->spm_irq_sta),
 110                        SPM_CORE_TIMEOUT);
 111                 return -1;
 112         }
 113
 114         write32(&mtk_spm->spm_cpu_wakeup_event, 0);
 115         write32(&mtk_spm->spm_wakeup_event_mask, con1);
 116         return 0;
 117 }
 118
 119 static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc)
 120 {
 121         u32 con1, pcm_fsm_sta;
 122
 123         if (read32(&mtk_spm->pcm_reg1_data) == SPM_PCM_REG1_DATA_CHECK &&
 124             read32(&mtk_spm->pcm_reg15_data) != SPM_PCM_REG15_DATA_CHECK) {
 125                 if (spm_code_swapping())
 126                         return -1;
 127                 write32(&mtk_spm->spm_power_on_val0,
 128                         read32(&mtk_spm->pcm_reg0_data));
 129         }
 130
 131         write32(&mtk_spm->pcm_pwr_io_en, 0);
 132
 133         clrsetbits32(&mtk_spm->pcm_con1,
 134                      PCM_TIMER_EN_LSB,
 135                      SPM_REGWR_CFG_KEY);
 136
 137         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
 138                 PCM_SW_RESET_LSB);
 139         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 140
 141         pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta);
 142
 143         if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) {
 144                 printk(BIOS_ERR, "reset pcm(PCM_FSM_STA=%#x)\n",
 145                        read32(&mtk_spm->pcm_fsm_sta));
 146                 return -1;
 147         }
 148
 149         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
 150                 EN_IM_SLEEP_DVS_LSB);
 151
 152         con1 = read32(&mtk_spm->pcm_con1) & PCM_WDT_WAKE_MODE_LSB;
 153         write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY |
 154                 EVENT_LOCK_EN_LSB | SPM_SRAM_ISOINT_B_LSB |
 155                 (pcmdesc->replace ? 0 : IM_NONRP_EN_LSB) |
 156                 MIF_APBEN_LSB | SCP_APB_INTERNAL_EN_LSB);
 157
 158         return 0;
 159 }
 160
 161 static void spm_load_pcm_code(const struct dyna_load_pcm *pcm)
 162 {
 163         int i;
 164
 165         write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
 166                 SPM_REGWR_CFG_KEY | IM_SLAVE_LSB);
 167
 168         for (i = 0; i < pcm->desc.size; i++) {
 169                 write32(&mtk_spm->pcm_im_host_rw_ptr,
 170                         PCM_IM_HOST_EN_LSB | PCM_IM_HOST_W_EN_LSB | i);
 171                 write32(&mtk_spm->pcm_im_host_rw_dat,
 172                         (u32) *(pcm->buf + i));
 173         }
 174         write32(&mtk_spm->pcm_im_host_rw_ptr, 0);
 175 }
 176
 177 static void spm_check_pcm_code(const struct dyna_load_pcm *pcm)
 178 {
 179         int i;
 180
 181         for (i = 0; i < pcm->desc.size; i++) {
 182                 write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | i);
 183                 if ((read32(&mtk_spm->pcm_im_host_rw_dat)) !=
 184                         (u32) *(pcm->buf + i))
 185                         spm_load_pcm_code(pcm);
 186         }
 187         write32(&mtk_spm->pcm_im_host_rw_ptr, 0);
 188 }
 189
 190 static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
 191 {
 192         u32 con0;
 193
 194         spm_load_pcm_code(pcm);
 195         spm_check_pcm_code(pcm);
 196
 197         printk(BIOS_DEBUG, "%s: ptr = %p\n", __func__, pcm->buf);
 198         printk(BIOS_DEBUG, "%s: len = %d\n", __func__, pcm->desc.size);
 199
 200         con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB);
 201         write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY |
 202                 PCM_CK_EN_LSB | IM_KICK_L_LSB);
 203         write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 204 }
 205
 206 static void spm_init_pcm_register(void)
 207 {
 208         write32(&mtk_spm->pcm_reg_data_ini,
 209                 read32(&mtk_spm->spm_power_on_val0));
 210         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
 211         write32(&mtk_spm->pcm_pwr_io_en, 0);
 212
 213         write32(&mtk_spm->pcm_reg_data_ini,
 214                 read32(&mtk_spm->spm_power_on_val1));
 215         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
 216         write32(&mtk_spm->pcm_pwr_io_en, 0);
 217 }
 218
 219 static void spm_init_event_vector(const struct pcm_desc *pcmdesc)
 220 {
 221         for (int i = 0; i < PCM_EVENT_VECTOR_NUM; i++)
 222                 write32(&mtk_spm->pcm_event_vector[i], pcmdesc->vector[i]);
 223 }
 224
 225 static const char * const dyna_load_pcm_path[] = {
 226         [DYNA_LOAD_PCM_SUSPEND_LP4_3733] = "pcm_allinone_lp4_3733.bin",
 227         [DYNA_LOAD_PCM_SUSPEND_LP4_3200] = "pcm_allinone_lp4_3200.bin",
 228 };
 229
 230 static int spm_load_firmware(enum dyna_load_pcm_index index,
 231                              struct dyna_load_pcm *pcm)
 232 {
 233         /*
 234          * Layout:
 235          *   u16 firmware_size
 236          *   u32 binary[firmware_size]
 237          *   struct pcm_desc descriptor
 238          *   char *version
 239          */
 240         u16 firmware_size;
 241         int copy_size;
 242         const char *file_name = dyna_load_pcm_path[index];
 243         struct stopwatch sw;
 244
 245         stopwatch_init(&sw);
 246
 247         size_t file_size = cbfs_boot_load_file(file_name, spm_bin,
 248                                                sizeof(spm_bin), CBFS_TYPE_RAW);
 249
 250         if (file_size == 0) {
 251                 printk(BIOS_ERR, "SPM binary %s not found\n", file_name);
 252                 return -1;
 253         }
 254
 255         int offset = 0;
 256
 257         /* firmware size */
 258         copy_size = sizeof(firmware_size);
 259         memcpy(&firmware_size, spm_bin + offset, copy_size);
 260         printk(BIOS_DEBUG, "SPM: binary array size = %d\n", firmware_size);
 261         offset += copy_size;
 262
 263         /* binary */
 264         assert(offset < file_size);
 265         copy_size = firmware_size * 4;
 266         pcm->buf = (u32 *)(spm_bin + offset);
 267         offset += copy_size;
 268
 269         /* descriptor */
 270         assert(offset < file_size);
 271         copy_size = sizeof(struct pcm_desc);
 272         memcpy((void *)&(pcm->desc.size), spm_bin + offset, copy_size);
 273         offset += copy_size;
 274
 275         /* version */
 276         /* The terminating character should be contained in the spm binary */
 277         assert(spm_bin[file_size - 1] == '\0');
 278         assert(offset < file_size);
 279         printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset);
 280
 281         printk(BIOS_INFO, "SPM binary loaded in %ld msecs\n",
 282                stopwatch_duration_msecs(&sw));
 283
 284         return 0;
 285 }
 286
 287 static void spm_kick_pcm_to_run(void)
 288 {
 289         uint32_t con0;
 290
 291         write32(&mtk_spm->spm_mas_pause_mask_b, SPM_MAS_PAUSE_MASK_B_VAL);
 292         write32(&mtk_spm->spm_mas_pause2_mask_b, SPM_MAS_PAUSE2_MASK_B_VAL);
 293         write32(&mtk_spm->pcm_reg_data_ini, 0);
 294
 295         write32(&mtk_spm->pcm_pwr_io_en, PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7);
 296
 297         printk(BIOS_DEBUG, "SPM: %s\n", __func__);
 298
 299         /* check IM ready */
 300         while ((read32(&mtk_spm->pcm_fsm_sta) & IM_STATE_MASK) != IM_STATE)
 301                 ;
 302
 303         /* kick PCM to run, and toggle PCM_KICK */
 304         con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB);
 305         write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
 306                 PCM_KICK_L_LSB);
 307         write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 308
 309         printk(BIOS_DEBUG, "SPM: %s done\n", __func__);
 310 }
 311
 312 int spm_init(void)
 313 {
 314         struct pcm_desc *pcmdesc;
 315         enum dyna_load_pcm_index index;
 316         struct stopwatch sw;
 317
 318         stopwatch_init(&sw);
 319
 320         if (CONFIG(MT8183_DRAM_EMCP))
 321                 index = DYNA_LOAD_PCM_SUSPEND_LP4_3733;
 322         else
 323                 index = DYNA_LOAD_PCM_SUSPEND_LP4_3200;
 324
 325         printk(BIOS_DEBUG, "SPM: pcm index = %d\n", index);
 326
 327         struct dyna_load_pcm pcm;
 328         if (spm_load_firmware(index, &pcm)) {
 329                 printk(BIOS_ERR, "SPM: firmware is not ready\n");
 330                 printk(BIOS_ERR, "SPM: check dram type and firmware version\n");
 331                 return -1;
 332         }
 333
 334         pcmdesc = &pcm.desc;
 335
 336         if (spm_register_init())
 337                 return -1;
 338
 339         if (spm_reset_and_init_pcm(pcmdesc))
 340                 return -1;
 341
 342         spm_kick_im_to_fetch(&pcm);
 343         spm_init_pcm_register();
 344         spm_init_event_vector(pcmdesc);
 345         spm_kick_pcm_to_run();
 346
 347         printk(BIOS_INFO, "SPM: %s done in %ld msecs\n", __func__,
 348                stopwatch_duration_msecs(&sw));
 349
 350         return 0;
 351 }